[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Chad Rosier via llvm-commits]

mcrosier added a comment.

In https://reviews.llvm.org/D21571#555504, @mcrosier wrote:

> Perhaps I missed this, but how is the pass being enabled for *only* Exynos?  AFAICT, it's enabled for all AArch64 targets.


I think Sebastian answered my question indirectly; the instructions cost of Exynos-M1 triggers the transform.

I would prefer we also have a target feature (as was done in the first version of the patch) that early exits runOnMachineFunction for non-Exynos-M1 subtargets.  Otherwise, we're doing a lot of unnecessary work (i.e., switching over every instruction in the function) for non-Exynos-M1 subtargets.


https://reviews.llvm.org/D21571