[PATCH] D25007: [DAG] Teach computeKnownBits and ComputeNumSignBits in SelectionDAG to look through EXTRACT_VECTOR_ELT.

[Bjorn Pettersson via llvm-commits]

bjope created this revision.
bjope added reviewers: bogner, mkuper.
bjope added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nhaehnle, jyknight.

Both computeKnownBits and ComputeNumSignBits can now do a simple look-through of EXTRACT_VECTOR_ELT. It will compute the result based on the known bits (or known sign bits) for the vector that the element is extracted from.


https://reviews.llvm.org/D25007

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  test/CodeGen/SPARC/vector-extract-elt.ll
  test/CodeGen/X86/pr21792.ll

Index: test/CodeGen/X86/pr21792.ll
===================================================================
--- test/CodeGen/X86/pr21792.ll
+++ test/CodeGen/X86/pr21792.ll
@@ -34,8 +34,8 @@
 ; CHECK-LABEL: func:
 ; CHECK: pextrq  $1, %xmm0,
 ; CHECK-NEXT: movd    %xmm0, %r[[AX:..]]
-; CHECK-NEXT: movslq  %e[[AX]],
-; CHECK-NEXT: sarq    $32, %r[[AX]]
+; CHECK-NEXT: movq    %r[[AX]],
+; CHECK-NEXT: shrq    $32, %r9
 }
 
 declare void @toto(double*, double*, double*, double*, double*, double*)
Index: test/CodeGen/SPARC/vector-extract-elt.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SPARC/vector-extract-elt.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+
+
+; If computeKnownBits/computeKnownSignBits (in SelectionDAG) can do a simple
+; look-thru for extractelement then we we know that the add will yield a
+; non-negative result.
+define i1 @test1(<4 x i16>* %in) {
+; CHECK-LABEL: ! BB#0:
+; CHECK-NEXT:        retl
+; CHECK-NEXT:        sethi 0, %o0
+  %vec2 = load <4 x i16>, <4 x i16>* %in, align 1
+  %vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
+  %vec4 = sext <4 x i16> %vec3 to <4 x i32>
+  %elt0 = extractelement <4 x i32> %vec4, i32 0
+  %elt1 = extractelement <4 x i32> %vec4, i32 1
+  %sum = add i32 %elt0, %elt1
+  %bool = icmp slt i32 %sum, 0
+  ret i1 %bool
+}
Index: test/CodeGen/AMDGPU/amdgpu.private-memory.ll
===================================================================
--- test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+++ test/CodeGen/AMDGPU/amdgpu.private-memory.ll
@@ -229,7 +229,8 @@
 
 ; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x68,0xe0
 ; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:2 ; encoding: [0x02,0x10,0x68,0xe0
-; SI-PROMOTE: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
+; Loaded value is 0 or 1, so sext will become zext, so we get buffer_load_ushort instead of buffer_load_sshort.
+; SI-PROMOTE: buffer_load_ushort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
 define void @short_array(i32 addrspace(1)* %out, i32 %index) #0 {
 entry:
   %0 = alloca [2 x i16]
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2448,6 +2448,22 @@
     KnownOne = KnownOne.trunc(BitWidth);
     break;
   }
+  case ISD::EXTRACT_VECTOR_ELT: {
+    const unsigned BitWidth = Op.getValueSizeInBits();
+    const unsigned EltBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
+    // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
+    // anything about the extended bits.
+    if (BitWidth > EltBitWidth) {
+      KnownZero = KnownZero.trunc(EltBitWidth);
+      KnownOne = KnownOne.trunc(EltBitWidth);
+    }
+    computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
+    if (BitWidth > EltBitWidth) {
+      KnownZero = KnownZero.zext(BitWidth);
+      KnownOne = KnownOne.zext(BitWidth);
+    }
+    break;
+  }
   case ISD::BSWAP: {
     computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
     KnownZero = KnownZero2.byteSwap();
@@ -2715,6 +2731,16 @@
     // result. Otherwise it gives either negative or > bitwidth result
     return std::max(std::min(KnownSign - rIndex * BitWidth, BitWidth), 0);
   }
+  case ISD::EXTRACT_VECTOR_ELT: {
+    const unsigned BitWidth = Op.getValueSizeInBits();
+    const unsigned EltBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
+    // If BitWidth > EltBitWidth the value is anyext:ed, and we do not know
+    // anything about sign bits. But if the sizes match we can derive knowledge
+    // about sign bits from the vector operand.
+    if (BitWidth == EltBitWidth)
+      return ComputeNumSignBits(Op.getOperand(0), Depth+1);
+    break;
+  }
   }
 
   // If we are looking at the loaded value of the SDNode.


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