[PATCH] D24681: Optimize patterns of vectorized interleaved memory accesses for X86.

[Zvi Rackover via llvm-commits]

zvi added a comment.

Some minor comments


================
Comment at: lib/Target/X86/X86InterleavedAccess.cpp:33
@@ +32,3 @@
+  // 64 bits on AVX2.
+  if (!SubTarget.hasAVX() ||
+      ShuffleVecSize != 256 ||
----------------
Need to check that Factor==4?
What about checking load size?

================
Comment at: lib/Target/X86/X86InterleavedAccess.cpp:79
@@ +78,3 @@
+  assert(DL.getTypeSizeInBits(LI->getType()) == Factor * ShuffleVecSize &&
+         "Unexpected number of elements in the load instruction");
+
----------------

unexpected load size

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Comment at: lib/Target/X86/X86InterleavedAccess.cpp:91
@@ +90,3 @@
+  // Generate 4 loads of type v4xT64
+  for (unsigned Part = 0; Part < Factor; Part++) {
+    Value *NewBasePtr = Builder.CreateGEP(
----------------
>From this point, is the code hard coded' for Factor==4? Maybe replacing occurrences of Factor with literal '4' will make it more obvious until we support more cases?


https://reviews.llvm.org/D24681