[PATCH] D22696: [CodeGenPrep] Skip merging empty case blocks

[David Li via llvm-commits]

davidxl added a comment.

Given the limitation of MachineSink pass to split critical edges later (for the switch case), the effect of creating critical edge in CGP here can be quite detrimental, so we should probably make the patch more general -- instead of checking just switch inst in Predecessor, check indirect branch as well.   Perhaps also adding some cost related heuristic -- by checking the number of phis (with incoming value from Pred) in the Succ block.

Here is what happens In this particular case:

    BB#7                   <--- indirect branch with jump table
  /      \       \

BB4  BB5  EB
 |        |      /
 \       |     /

  BB2

EB gets eliminated by CGP

  BB#7                   <--- indirect branch with jump table
  /      \       \

BB4  BB5  |
 |        |      /
 \       |     /

  BB2

BB#2:

  %vreg8<def> = PHI %vreg33, <BB#7>, %vreg19, d<BB#10>, ....
   %vreg9<def> = PHI %vreg34, <BB#7>, %vreg48, <BB#10>, ....
   %vreg10<def> = PHI %vreg35, <BB#7>, %vreg2, <BB#10>, ...
   %vreg11<def> = PHI %vreg36, <BB#7>, %vreg1, <BB#10>,  ....

BB#7:

  %vreg36<def> = COPY %vreg38; GPR64all:%vreg36 GPR64:%vreg38
   %vreg35<def> = COPY %vreg39; GPR64all:%vreg35 GPR64:%vreg39
   %vreg33<def> = COPY %vreg40; GPR32all:%vreg33 GPR32:%vreg40
   %vreg34<def> = SUBREG_TO_REG 0, %vreg41, 15; GPR64all:%vreg34 GPR32:%vreg41
   %vreg43<def> = SUBREG_TO_REG 0, %vreg44<kill>, 15; GPR64:%vreg43 GPR32common:%vreg44
   %vreg47<def> = LDRXroX %vreg46, %vreg43<kill>, 0, 1; mem:LD8[JumpTable] GPR64:%vreg47,%vreg43 GPR64common:%vreg46
   BR %vreg47<kill>; GPR64:%vreg47

After PHI elimination, due to the critical edge, BB#7 ends up with many copy instructions:

BB#2:

   %vreg11<def> = COPY %vreg84<kill>; GPR64:%vreg11,%vreg84
  %vreg10<def> = COPY %vreg83<kill>; GPR64:%vreg10,%vreg83
  %vreg9<def> = COPY %vreg82<kill>; GPR64:%vreg9,%vreg82
  %vreg8<def> = COPY %vreg81<kill>; GPR32all:%vreg8,%vreg81
  
   ....

BB#7:

  %vreg81<def> = COPY %vreg33<kill>; GPR32all:%vreg81,%vreg33
     %vreg82<def> = COPY %vreg34<kill>; GPR64:%vreg82 GPR64all:%vreg34
     %vreg83<def> = COPY %vreg35<kill>; GPR64:%vreg83 GPR64all:%vreg35
     %vreg84<def> = COPY %vreg36<kill>; GPR64:%vreg84 GPR64all:%vreg36
     %vreg85<def> = COPY %vreg19; GPR32all:%vreg85 GPR32sp:%vreg19
     %vreg86<def> = COPY %vreg5; GPR64all:%vreg86,%vreg5
     %vreg87<def> = COPY %vreg2; GPR64all:%vreg87,%vreg2
     %vreg88<def> = COPY %vreg1; GPR64all:%vreg88,%vreg1

Some of these copy instructions which can not be sinked into less frequent path (due to failure in critical edge split) later become the address computation ADRP/MOV during virtual register rewrite.


https://reviews.llvm.org/D22696