[llvm] r282273 - ScheduleDAG: Match enum names when printing sdep kinds
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 23 11:28:32 PDT 2016
Author: matze
Date: Fri Sep 23 13:28:31 2016
New Revision: 282273
URL: http://llvm.org/viewvc/llvm-project?rev=282273&view=rev
Log:
ScheduleDAG: Match enum names when printing sdep kinds
It is less confusing to have the same names in the debug print as the
enum members.
Modified:
llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
llvm/trunk/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Fri Sep 23 13:28:31 2016
@@ -337,10 +337,10 @@ void SUnit::dumpAll(const ScheduleDAG *G
I != E; ++I) {
dbgs() << " ";
switch (I->getKind()) {
- case SDep::Data: dbgs() << "val "; break;
- case SDep::Anti: dbgs() << "anti"; break;
- case SDep::Output: dbgs() << "out "; break;
- case SDep::Order: dbgs() << "ch "; break;
+ case SDep::Data: dbgs() << "data "; break;
+ case SDep::Anti: dbgs() << "anti "; break;
+ case SDep::Output: dbgs() << "out "; break;
+ case SDep::Order: dbgs() << "ord "; break;
}
dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
if (I->isArtificial())
@@ -357,10 +357,10 @@ void SUnit::dumpAll(const ScheduleDAG *G
I != E; ++I) {
dbgs() << " ";
switch (I->getKind()) {
- case SDep::Data: dbgs() << "val "; break;
- case SDep::Anti: dbgs() << "anti"; break;
- case SDep::Output: dbgs() << "out "; break;
- case SDep::Order: dbgs() << "ch "; break;
+ case SDep::Data: dbgs() << "data "; break;
+ case SDep::Anti: dbgs() << "anti "; break;
+ case SDep::Output: dbgs() << "out "; break;
+ case SDep::Order: dbgs() << "ord "; break;
}
dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
if (I->isArtificial())
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll Fri Sep 23 13:28:31 2016
@@ -13,9 +13,9 @@
; CHECK: SU(2): STRWui %WZR
; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP
; CHECK: Predecessors:
-; CHECK-NEXT: out SU(0)
-; CHECK-NEXT: out SU(0)
-; CHECK-NEXT: ch SU(0)
+; CHECK-NEXT: out SU(0)
+; CHECK-NEXT: out SU(0)
+; CHECK-NEXT: ord SU(0)
; CHECK-NEXT: Successors:
define void @test1() {
entry:
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll Fri Sep 23 13:28:31 2016
@@ -8,8 +8,8 @@
; CHECK: shiftable
; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
; CHECK: Successors:
-; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
-; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
+; CHECK-NEXT: data SU(4): Latency=1 Reg=%vreg2
+; CHECK-NEXT: data SU(3): Latency=2 Reg=%vreg2
; CHECK: ********** INTERVALS **********
define i64 @shiftable(i64 %A, i64 %B) {
%tmp0 = sub i64 %B, 20
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll Fri Sep 23 13:28:31 2016
@@ -7,11 +7,11 @@
; CHECK: misched_bug:BB#0 entry
; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
; CHECK: Successors:
-; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2
-; CHECK-NEXT: ch SU(4): Latency=0
+; CHECK-NEXT: data SU(5): Latency=4 Reg=%vreg2
+; CHECK-NEXT: ord SU(4): Latency=0
; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
; CHECK: Successors:
-; CHECK: ch SU(4): Latency=0
+; CHECK: ord SU(4): Latency=0
; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2
; CHECK: ** ScheduleDAGMI::schedule picking next node
Modified: llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll Fri Sep 23 13:28:31 2016
@@ -37,8 +37,8 @@ declare void @callee2(i8*, i8*, i8*, i8*
; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
; CHECK-NOT: SU
; CHECK: Successors:
-; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0
-; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0
+; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0
+; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0
; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
Modified: llvm/trunk/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll?rev=282273&r1=282272&r2=282273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll Fri Sep 23 13:28:31 2016
@@ -6,23 +6,23 @@
; CHECK: ** List Scheduling
; CHECK: SU(2){{.*}}STR{{.*}}Volatile
-; CHECK-NOT: ch SU
-; CHECK: ch SU(3): Latency=1
-; CHECK-NOT: ch SU
+; CHECK-NOT: ord SU
+; CHECK: ord SU(3): Latency=1
+; CHECK-NOT: ord SU
; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
-; CHECK-NOT: ch SU
-; CHECK: ch SU(2): Latency=1
-; CHECK-NOT: ch SU
+; CHECK-NOT: ord SU
+; CHECK: ord SU(2): Latency=1
+; CHECK-NOT: ord SU
; CHECK: Successors:
; CHECK: ** List Scheduling
; CHECK: SU(2){{.*}}STR{{.*}}
-; CHECK-NOT: ch SU
-; CHECK: ch SU(3): Latency=1
-; CHECK-NOT: ch SU
+; CHECK-NOT: ord SU
+; CHECK: ord SU(3): Latency=1
+; CHECK-NOT: ord SU
; CHECK: SU(3){{.*}}LDR{{.*}}
-; CHECK-NOT: ch SU
-; CHECK: ch SU(2): Latency=1
-; CHECK-NOT: ch SU
+; CHECK-NOT: ord SU
+; CHECK: ord SU(2): Latency=1
+; CHECK-NOT: ord SU
; CHECK: Successors:
define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
entry:
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