[PATCH] D23614: [PPC] Generate positive FP zero using xor insn instead of loading from constant area

[Kit Barton via llvm-commits]

kbarton requested changes to this revision.
kbarton added a comment.
This revision now requires changes to proceed.

We need to handle fp16 and fp80, or at least document why they are omitted.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12121
@@ +12120,3 @@
+
+bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+
----------------
I agree with Eric. I think a general comment would be useful here. Something like: Single-precision and double precision FP immediates can be loaded when VSX instructions are available and the Immediate has value 0. Half-precision and 80-bit are excluded because...


================
Comment at: test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll:5
@@ -4,3 +4,3 @@
 ; CHECK-LABEL: TestULT:
-; CHECK: mcrf
+; CHECK: xscmpudp
 ; CHECK: blr
----------------
Any insight from git blame?


https://reviews.llvm.org/D23614