[PATCH] D24747: [AArch64] Improve isel of negate of zext.

[Geoff Berry via llvm-commits]

gberry added a comment.

In https://reviews.llvm.org/D24747#547343, @t.p.northover wrote:

> Aren't other instructions affected too? Add at least ought to be symmetric, and quite possibly some logical operations.


I believe ADD/ADDS are the only other instructions with UXTW forms.  I didn't think those would be interesting since they shouldn't ever have a known 0 as an operand, but I tried it anyway, and it does end up making a difference (by, for example, generating more madds).  I'm still working on tinkering with the AddedComplexity and adding more patterns to avoid regressions, but this should end up having more of an impact than I initially thought.


https://reviews.llvm.org/D24747