[PATCH] D24747: [AArch64] Improve isel of negate of zext.

[Chad Rosier via llvm-commits]

mcrosier added a comment.

LGTM, but I'd be interested to hear feedback from @jmolloy or @t.p.northover.


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Comment at: lib/Target/AArch64/AArch64InstrInfo.td:313
@@ -312,1 +312,3 @@
 
+// Any instruction that defines a 32-bit result leaves the high half of the
+// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
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Not your fault, but maybe fix the wording of the first sentence.. 

"..leaves the high half of the register zeroed."

Feel free to commit as a separate patch.



https://reviews.llvm.org/D24747