[llvm] r281733 - [AArch64][GlobalISel] Add tests for default RegBank mappings. NFC.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 07:44:48 PDT 2016
Author: ab
Date: Fri Sep 16 09:44:48 2016
New Revision: 281733
URL: http://llvm.org/viewvc/llvm-project?rev=281733&view=rev
Log:
[AArch64][GlobalISel] Add tests for default RegBank mappings. NFC.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir?rev=281733&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Fri Sep 16 09:44:48 2016
@@ -0,0 +1,371 @@
+# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
+
+# Check the default mappings for various instructions.
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @test_add_s32() { ret void }
+ define void @test_add_v4s32() { ret void }
+ define void @test_sub_s32() { ret void }
+ define void @test_sub_v4s32() { ret void }
+ define void @test_mul_s32() { ret void }
+ define void @test_mul_v4s32() { ret void }
+
+ define void @test_and_s32() { ret void }
+ define void @test_and_v4s32() { ret void }
+ define void @test_or_s32() { ret void }
+ define void @test_or_v4s32() { ret void }
+ define void @test_xor_s32() { ret void }
+ define void @test_xor_v4s32() { ret void }
+
+ define void @test_shl_s32() { ret void }
+ define void @test_shl_v4s32() { ret void }
+ define void @test_lshr_s32() { ret void }
+ define void @test_ashr_s32() { ret void }
+
+ define void @test_sdiv_s32() { ret void }
+ define void @test_udiv_s32() { ret void }
+...
+
+---
+# CHECK-LABEL: name: test_add_s32
+name: test_add_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_ADD %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_ADD %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_add_v4s32
+name: test_add_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_ADD %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_ADD %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_sub_s32
+name: test_sub_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_SUB %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_SUB %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_sub_v4s32
+name: test_sub_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_SUB %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_SUB %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_mul_s32
+name: test_mul_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_MUL %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_MUL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_mul_v4s32
+name: test_mul_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_MUL %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_MUL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_and_s32
+name: test_and_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_AND %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_AND %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_and_v4s32
+name: test_and_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_AND %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_AND %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_or_s32
+name: test_or_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_OR %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_OR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_or_v4s32
+name: test_or_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_OR %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_OR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_xor_s32
+name: test_xor_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_XOR %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_XOR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_xor_v4s32
+name: test_xor_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_XOR %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_XOR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_shl_s32
+name: test_shl_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_SHL %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_SHL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_shl_v4s32
+name: test_shl_v4s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %q0
+ ; CHECK: %0(<4 x s32>) = COPY %q0
+ ; CHECK: %1(<4 x s32>) = G_SHL %0, %0
+ %0(<4 x s32>) = COPY %q0
+ %1(<4 x s32>) = G_SHL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_lshr_s32
+name: test_lshr_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_LSHR %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_LSHR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_ashr_s32
+name: test_ashr_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_ASHR %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_ASHR %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_sdiv_s32
+name: test_sdiv_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_SDIV %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_SDIV %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_udiv_s32
+name: test_udiv_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s32) = G_UDIV %0, %0
+ %0(s32) = COPY %w0
+ %1(s32) = G_UDIV %0, %0
+...
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