[PATCH] D24631: [RFC] Implement variable-width register classes, step 1: API changes

[Alex Bradbury via llvm-commits]

asb added a comment.

Hi Krzysztof. So as discussed in https://reviews.llvm.org/D23561 the motivating problem for this work is cases (as in Hexagon HVX) where instructions with identical encodings currently need to be defined twice. An example of this is valignb <https://reviews.llvm.org/diffusion/L/browse/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td;281711$1884>. Having a register class with a non-constant register size and alignment would solve the issue for HVX, but there's also the hope it will be useful for other targets. For these HVX instructions there is no `list<dag> pattern` defined. If a pattern was specified, surely even with this new functionality you'd need to have repeated instruction definitions in order to define multiple patterns given the pattern would need different `ValueType`s? Do you have something in mind that would address this as well?


Repository:
  rL LLVM

https://reviews.llvm.org/D24631