[PATCH] D24366: [MachineCombiner] Support for floating-point FMA under the FPOpFusion Fast flag on ARM64

[Evandro Menezes via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL281649: [AArch64] Support for FP FMA when -ffp-contract=fast (authored by evandro).

Changed prior to commit:
  https://reviews.llvm.org/D24366?vs=70757&id=71539#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24366

Files:
  llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll

Index: llvm/trunk/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -fp-contract=fast | FileCheck %s
+define float @mul_add(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: %entry
+; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+  entry:
+    %mul = fmul float %a, %b
+    %add = fadd float %mul, %c
+    ret float %add
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2901,6 +2901,8 @@
 // FP Opcodes that can be combined with a FMUL
 static bool isCombineInstrCandidateFP(const MachineInstr &Inst) {
   switch (Inst.getOpcode()) {
+  default:
+    break;
   case AArch64::FADDSrr:
   case AArch64::FADDDrr:
   case AArch64::FADDv2f32:
@@ -2911,9 +2913,9 @@
   case AArch64::FSUBv2f32:
   case AArch64::FSUBv2f64:
   case AArch64::FSUBv4f32:
-    return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
-  default:
-    break;
+		TargetOptions Options = Inst.getParent()->getParent()->getTarget().Options; 
+    return (Options.UnsafeFPMath || 
+				    Options.AllowFPOpFusion == FPOpFusion::Fast);
   }
   return false;
 }


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