[PATCH] D24577: [RFC] Move synchronization scope and atomic orderings from SDNode to MachineMemOperand

[Konstantin Zhuravlyov via llvm-commits]

kzhuravl created this revision.
kzhuravl added reviewers: arsenm, tstellarAMD.
kzhuravl added subscribers: mehdi_amini, reames, jlebar, tony-tye, sheredom, PFerreira, llvm-commits.
Herald added a subscriber: wdng.

+ remove redundant getAtomic* member functions from SelectionDAG.

In order to implement memory model in AMDGPU backend, we need to generate a specific sequence of instructions depending on atomic ordering and synchronization scope. These instructions have to stick together, for example:

```
...
%val = load atomic i32, i32 addrspace(4)* %in acquire, align 4
...
```

Results in:
```
...
s_waitcnt
flat_load_dword ...
s_waitcnt
buffer_wbinvl1_vol
...
```

One approach in implementing this is to use pseudo instructions, and expand them into real instructions in the post-RA expansion pass. The problem we have run into with this approach in AMDGPU backend is we have to define quite a lot of pseudo instructions due to having multiple different instruction opcodes for loads and stores.

Another approach we have explored is to move AtomicOrdering and SynchScope from MemSDNode and AtomicSDNode into MachineMemOperand. This way we do not have to define multiple pseudo instructions, and just use MachineMemOperand. There is also a fixme comment that suggests the same approach.

https://reviews.llvm.org/D24577

Files:
  include/llvm/CodeGen/MachineFunction.h
  include/llvm/CodeGen/MachineMemOperand.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  lib/CodeGen/MachineFunction.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp

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