[PATCH] D23561: [RISCV 4/10] Add basic RISCV{InstrFormats, InstrInfo, RegisterInfo, }.td

[David Chisnall via llvm-commits]

theraven added a comment.

In https://reviews.llvm.org/D23561#542479, @kparzysz wrote:

> In https://reviews.llvm.org/D23561#542222, @asb wrote:
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> >
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> On a somewhat longer-term note:
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> We have the exact same situation with HVX: the vector registers can be 64 or 128-byte long, depending on the processor mode. The actual encodings are identical between the two modes, so it's possible to have a single binary that would work in both modes. We have every HVX instruction defined twice, and separate register classes for both types of registers. This is a pain and a mess, and I have been planning to get rid of that for quite some time now.
>
> Since this type of situation now appears in several targets, I hope that this will be enough of a rationale to develop a proper support for this issue, namely register class with a non-constant register size/alignment.  This should be fairly simple, actually, and I can develop a prototype for review, hopefully in a few days.


Please add me to the review thread for this.  We have the same thing in MIPS and it's even worse in CHERI (where we have 128- and 256-bit variants of the ISA and currently conditionally compile for only one of them).


https://reviews.llvm.org/D23561