[PATCH] D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc

[James Y Knight via llvm-commits]

jyknight accepted this revision.
This revision is now accepted and ready to land.

================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp:22
@@ +21,3 @@
+  PointerSize = CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4;
+  CommentString = "#";
+  AlignmentIsInBytes = false;
----------------
No, it doesn't. We spill according to the register class size.

This value seems only to be used in lib/MC/MCDwarf.cpp, for emitting CFI instructions -- and that use case seems like it's just a factor written to the CIE which all the CFI instructions get multiplied by.


https://reviews.llvm.org/D23562