[llvm] r281249 - [MC] Defer asm errors to post-statement failure
Nirav Dave via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 12 13:03:03 PDT 2016
Author: niravd
Date: Mon Sep 12 15:03:02 2016
New Revision: 281249
URL: http://llvm.org/viewvc/llvm-project?rev=281249&view=rev
Log:
[MC] Defer asm errors to post-statement failure
Allow errors to be deferred and emitted as part of clean up to simplify
and shorten Assembly parser code. This will allow error messages to be
emitted in helper functions and be modified by the caller which has
better context.
As part of this many minor cleanups to the Parser:
* Unify parser cleanup on error
* Add Workaround for incorrect return values in ParseDirective instances
* Tighten checks on error-signifying return values for parser functions
and fix in-tree TargetParsers to be more consistent with the changes.
* Fix AArch64 test cases checking for spurious error messages that are
now fixed.
These changes should be backwards compatible with current Target Parsers
so long as the error status are correctly returned in appropriate
functions.
Reviewers: rnk, majnemer
Subscribers: aemerson, jyknight, llvm-commits
Differential Revision: https://reviews.llvm.org/D24047
Modified:
llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h
llvm/trunk/include/llvm/Support/SMLoc.h
llvm/trunk/lib/MC/MCParser/AsmParser.cpp
llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp
llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s
llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s
llvm/trunk/test/MC/AArch64/neon-diagnostics.s
Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Mon Sep 12 15:03:02 2016
@@ -144,6 +144,7 @@ protected: // Can only create subclasses
const char *TokStart;
bool SkipSpace;
bool AllowAtInIdentifier;
+ bool IsAtStartOfStatement;
MCAsmLexer();
@@ -163,6 +164,8 @@ public:
/// the main input file has been reached.
const AsmToken &Lex() {
assert(!CurTok.empty());
+ // Mark if we parsing out a EndOfStatement.
+ IsAtStartOfStatement = CurTok.front().getKind() == AsmToken::EndOfStatement;
CurTok.erase(CurTok.begin());
// LexToken may generate multiple tokens via UnLex but will always return
// the first one. Place returned value at head of CurTok vector.
@@ -174,9 +177,12 @@ public:
}
void UnLex(AsmToken const &Token) {
+ IsAtStartOfStatement = false;
CurTok.insert(CurTok.begin(), Token);
}
+ bool isAtStartOfStatement() { return IsAtStartOfStatement; }
+
virtual StringRef LexUntilEndOfStatement() = 0;
/// Get the current source location.
Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Sep 12 15:03:02 2016
@@ -11,7 +11,9 @@
#define LLVM_MC_MCPARSER_MCASMPARSER_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/Support/DataTypes.h"
@@ -67,6 +69,12 @@ public:
typedef std::pair<MCAsmParserExtension*, DirectiveHandler>
ExtensionDirectiveHandler;
+ struct MCPendingError {
+ SMLoc Loc;
+ SmallString<64> Msg;
+ SMRange Range;
+ };
+
private:
MCAsmParser(const MCAsmParser &) = delete;
void operator=(const MCAsmParser &) = delete;
@@ -78,6 +86,11 @@ private:
protected: // Can only create subclasses.
MCAsmParser();
+ bool HadError;
+
+ SmallVector<MCPendingError, 1> PendingErrors;
+ /// Flag tracking whether any errors have been encountered.
+
public:
virtual ~MCAsmParser();
@@ -122,21 +135,36 @@ public:
const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0;
/// \brief Emit a note at the location \p L, with the message \p Msg.
- virtual void Note(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) = 0;
+ virtual void Note(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
/// \brief Emit a warning at the location \p L, with the message \p Msg.
///
/// \return The return value is true, if warnings are fatal.
- virtual bool Warning(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) = 0;
+ virtual bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
+
+ /// \brief Return an error at the location \p L, with the message \p Msg. This
+ /// may be modified before being emitted.
+ ///
+ /// \return The return value is always true, as an idiomatic convenience to
+ /// clients.
+ bool Error(SMLoc L, const Twine &Msg, SMRange Range = None);
/// \brief Emit an error at the location \p L, with the message \p Msg.
///
/// \return The return value is always true, as an idiomatic convenience to
/// clients.
- virtual bool Error(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) = 0;
+ virtual bool printError(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
+
+ bool hasPendingError() { return !PendingErrors.empty(); }
+
+ bool printPendingErrors() {
+ bool rv = !PendingErrors.empty();
+ for (auto Err : PendingErrors) {
+ printError(Err.Loc, Twine(Err.Msg), Err.Range);
+ }
+ PendingErrors.clear();
+ return rv;
+ }
/// \brief Get the next AsmToken in the stream, possibly handling file
/// inclusion first.
@@ -146,7 +174,7 @@ public:
const AsmToken &getTok() const;
/// \brief Report an error at the current lexer location.
- bool TokError(const Twine &Msg, ArrayRef<SMRange> Ranges = None);
+ bool TokError(const Twine &Msg, SMRange Range = None);
bool parseTokenLoc(SMLoc &Loc);
bool parseToken(AsmToken::TokenKind T, const Twine &Msg);
Modified: llvm/trunk/include/llvm/Support/SMLoc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SMLoc.h?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/SMLoc.h (original)
+++ llvm/trunk/include/llvm/Support/SMLoc.h Mon Sep 12 15:03:02 2016
@@ -15,6 +15,7 @@
#ifndef LLVM_SUPPORT_SMLOC_H
#define LLVM_SUPPORT_SMLOC_H
+#include "llvm/ADT/None.h"
#include <cassert>
namespace llvm {
@@ -50,6 +51,7 @@ public:
SMLoc Start, End;
SMRange() {}
+ SMRange(NoneType) : Start(), End() {}
SMRange(SMLoc St, SMLoc En) : Start(St), End(En) {
assert(Start.isValid() == End.isValid() &&
"Start and end should either both be valid or both be invalid!");
Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -178,9 +178,6 @@ private:
/// \brief Keeps track of how many .macro's have been instantiated.
unsigned NumOfMacroInstantiations;
- /// Flag tracking whether any errors have been encountered.
- unsigned HadError : 1;
-
/// The values from the last parsed cpp hash file line comment if any.
struct CppHashInfoTy {
StringRef Filename;
@@ -247,12 +244,9 @@ public:
AssemblerDialect = i;
}
- void Note(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) override;
- bool Warning(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) override;
- bool Error(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) override;
+ void Note(SMLoc L, const Twine &Msg, SMRange Range = None) override;
+ bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) override;
+ bool printError(SMLoc L, const Twine &Msg, SMRange Range = None) override;
const AsmToken &Lex() override;
@@ -337,7 +331,8 @@ private:
void printMacroInstantiations();
void printMessage(SMLoc Loc, SourceMgr::DiagKind Kind, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) const {
+ SMRange Range = None) const {
+ ArrayRef<SMRange> Ranges(Range);
SrcMgr.PrintMessage(Loc, Kind, Msg, Ranges);
}
static void DiagHandler(const SMDiagnostic &Diag, void *Context);
@@ -565,8 +560,8 @@ AsmParser::AsmParser(SourceMgr &SM, MCCo
const MCAsmInfo &MAI)
: Lexer(MAI), Ctx(Ctx), Out(Out), MAI(MAI), SrcMgr(SM),
PlatformParser(nullptr), CurBuffer(SM.getMainFileID()),
- MacrosEnabledFlag(true), HadError(false), CppHashInfo(),
- AssemblerDialect(~0U), IsDarwin(false), ParsingInlineAsm(false) {
+ MacrosEnabledFlag(true), CppHashInfo(), AssemblerDialect(~0U),
+ IsDarwin(false), ParsingInlineAsm(false) {
// Save the old handler.
SavedDiagHandler = SrcMgr.getDiagHandler();
SavedDiagContext = SrcMgr.getDiagContext();
@@ -609,24 +604,25 @@ void AsmParser::printMacroInstantiations
"while in macro instantiation");
}
-void AsmParser::Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
- printMessage(L, SourceMgr::DK_Note, Msg, Ranges);
+void AsmParser::Note(SMLoc L, const Twine &Msg, SMRange Range) {
+ printPendingErrors();
+ printMessage(L, SourceMgr::DK_Note, Msg, Range);
printMacroInstantiations();
}
-bool AsmParser::Warning(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
+bool AsmParser::Warning(SMLoc L, const Twine &Msg, SMRange Range) {
if(getTargetParser().getTargetOptions().MCNoWarn)
return false;
if (getTargetParser().getTargetOptions().MCFatalWarnings)
- return Error(L, Msg, Ranges);
- printMessage(L, SourceMgr::DK_Warning, Msg, Ranges);
+ return Error(L, Msg, Range);
+ printMessage(L, SourceMgr::DK_Warning, Msg, Range);
printMacroInstantiations();
return false;
}
-bool AsmParser::Error(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
+bool AsmParser::printError(SMLoc L, const Twine &Msg, SMRange Range) {
HadError = true;
- printMessage(L, SourceMgr::DK_Error, Msg, Ranges);
+ printMessage(L, SourceMgr::DK_Error, Msg, Range);
printMacroInstantiations();
return true;
}
@@ -731,32 +727,38 @@ bool AsmParser::Run(bool NoInitialTextSe
if (!parseStatement(Info, nullptr))
continue;
- // If we've failed, but on a Error Token, but did not consume it in
- // favor of a better message, emit it now.
- if (Lexer.getTok().is(AsmToken::Error)) {
+ // If we have a Lexer Error we are on an Error Token. Load in Lexer Error
+ // for printing ErrMsg via Lex() only if no (presumably better) parser error
+ // exists.
+ if (!hasPendingError() && Lexer.getTok().is(AsmToken::Error)) {
Lex();
}
- // We had an error, validate that one was emitted and recover by skipping to
- // the next line.
- assert(HadError && "Parse statement returned an error, but none emitted!");
- eatToEndOfStatement();
+ // parseStatement returned true so may need to emit an error.
+ printPendingErrors();
+
+ // Skipping to the next line if needed.
+ if (!getLexer().isAtStartOfStatement())
+ eatToEndOfStatement();
}
+ // All errors should have been emitted.
+ assert(!hasPendingError() && "unexpected error from parseStatement");
+
getTargetParser().flushPendingInstructions(getStreamer());
if (TheCondState.TheCond != StartingCondState.TheCond ||
TheCondState.Ignore != StartingCondState.Ignore)
- return TokError("unmatched .ifs or .elses");
-
+ printError(getTok().getLoc(), "unmatched .ifs or .elses");
// Check to see there are no empty DwarfFile slots.
const auto &LineTables = getContext().getMCDwarfLineTables();
if (!LineTables.empty()) {
unsigned Index = 0;
for (const auto &File : LineTables.begin()->second.getMCDwarfFiles()) {
if (File.Name.empty() && Index != 0)
- TokError("unassigned file number: " + Twine(Index) +
- " for .file directives");
+ printError(getTok().getLoc(), "unassigned file number: " +
+ Twine(Index) +
+ " for .file directives");
++Index;
}
}
@@ -776,9 +778,8 @@ bool AsmParser::Run(bool NoInitialTextSe
// FIXME: We would really like to refer back to where the symbol was
// first referenced for a source location. We need to add something
// to track that. Currently, we just point to the end of the file.
- HadError |=
- Error(getTok().getLoc(), "assembler local symbol '" +
- Sym->getName() + "' not defined");
+ printError(getTok().getLoc(), "assembler local symbol '" +
+ Sym->getName() + "' not defined");
}
}
@@ -789,7 +790,7 @@ bool AsmParser::Run(bool NoInitialTextSe
// Reset the state of any "# line file" directives we've seen to the
// context as it was at the diagnostic site.
CppHashInfo = std::get<1>(LocSym);
- HadError |= Error(std::get<0>(LocSym), "directional label undefined");
+ printError(std::get<0>(LocSym), "directional label undefined");
}
}
}
@@ -804,7 +805,8 @@ bool AsmParser::Run(bool NoInitialTextSe
void AsmParser::checkForValidSection() {
if (!ParsingInlineAsm && !getStreamer().getCurrentSection().first) {
- TokError("expected section directive before assembly directive");
+ printError(getTok().getLoc(),
+ "expected section directive before assembly directive");
Out.InitSections(false);
}
}
@@ -1435,6 +1437,7 @@ bool AsmParser::parseBinOpRHS(unsigned P
/// ::= Label* Identifier OperandList* EndOfStatement
bool AsmParser::parseStatement(ParseStatementInfo &Info,
MCAsmParserSemaCallback *SI) {
+ assert(!hasPendingError() && "parseStatement started with pending error");
// Eat initial spaces and comments
while (Lexer.is(AsmToken::Space))
Lex();
@@ -1467,15 +1470,19 @@ bool AsmParser::parseStatement(ParseStat
if (Lexer.is(AsmToken::Integer)) {
LocalLabelVal = getTok().getIntVal();
if (LocalLabelVal < 0) {
- if (!TheCondState.Ignore)
- return TokError("unexpected token at start of statement");
+ if (!TheCondState.Ignore) {
+ Lex(); // always eat a token
+ return Error(IDLoc, "unexpected token at start of statement");
+ }
IDVal = "";
} else {
IDVal = getTok().getString();
Lex(); // Consume the integer token to be used as an identifier token.
if (Lexer.getKind() != AsmToken::Colon) {
- if (!TheCondState.Ignore)
- return TokError("unexpected token at start of statement");
+ if (!TheCondState.Ignore) {
+ Lex(); // always eat a token
+ return Error(IDLoc, "unexpected token at start of statement");
+ }
}
}
} else if (Lexer.is(AsmToken::Dot)) {
@@ -1492,8 +1499,10 @@ bool AsmParser::parseStatement(ParseStat
Lex();
IDVal = "}";
} else if (parseIdentifier(IDVal)) {
- if (!TheCondState.Ignore)
- return TokError("unexpected token at start of statement");
+ if (!TheCondState.Ignore) {
+ Lex(); // always eat a token
+ return Error(IDLoc, "unexpected token at start of statement");
+ }
IDVal = "";
}
@@ -1655,9 +1664,20 @@ bool AsmParser::parseStatement(ParseStat
getTargetParser().flushPendingInstructions(getStreamer());
- // First query the target-specific parser. It will return 'true' if it
- // isn't interested in this directive.
- if (!getTargetParser().ParseDirective(ID))
+ SMLoc StartTokLoc = getTok().getLoc();
+ bool TPDirectiveReturn = getTargetParser().ParseDirective(ID);
+
+ if (hasPendingError())
+ return true;
+ // Currently the return value should be true if we are
+ // uninterested but as this is at odds with the standard parsing
+ // convention (return true = error) we have instances of a parsed
+ // directive that fails returning true as an error. Catch these
+ // cases as best as possible errors here.
+ if (TPDirectiveReturn && StartTokLoc != getTok().getLoc())
+ return true;
+ // Return if we did some parsing or believe we succeeded.
+ if (!TPDirectiveReturn || StartTokLoc != getTok().getLoc())
return false;
// Next, check the extension directive map to see if any extension has
@@ -1912,9 +1932,9 @@ bool AsmParser::parseStatement(ParseStat
// Canonicalize the opcode to lower case.
std::string OpcodeStr = IDVal.lower();
ParseInstructionInfo IInfo(Info.AsmRewrites);
- bool HadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
- Info.ParsedOperands);
- Info.ParseError = HadError;
+ bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+ Info.ParsedOperands);
+ Info.ParseError = ParseHadError;
// Dump the parsed representation, if requested.
if (getShowParsedOperands()) {
@@ -1931,9 +1951,13 @@ bool AsmParser::parseStatement(ParseStat
printMessage(IDLoc, SourceMgr::DK_Note, OS.str());
}
+ // Fail even if ParseInstruction erroneously returns false.
+ if (hasPendingError() || ParseHadError)
+ return true;
+
// If we are generating dwarf for the current section then generate a .loc
// directive for the instruction.
- if (!HadError && getContext().getGenDwarfForAssembly() &&
+ if (!ParseHadError && getContext().getGenDwarfForAssembly() &&
getContext().getGenDwarfSectionSyms().count(
getStreamer().getCurrentSection().first)) {
unsigned Line;
@@ -1975,15 +1999,13 @@ bool AsmParser::parseStatement(ParseStat
}
// If parsing succeeded, match the instruction.
- if (!HadError) {
+ if (!ParseHadError) {
uint64_t ErrorInfo;
- getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode,
- Info.ParsedOperands, Out,
- ErrorInfo, ParsingInlineAsm);
+ if (getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode,
+ Info.ParsedOperands, Out,
+ ErrorInfo, ParsingInlineAsm))
+ return true;
}
-
- // Don't skip the rest of the line, the instruction parser is responsible for
- // that.
return false;
}
@@ -2019,6 +2041,7 @@ bool AsmParser::parseCppHashLineFilename
"Lexing Cpp line comment: Expected String");
StringRef Filename = getTok().getString();
Lex();
+
// Get rid of the enclosing quotes.
Filename = Filename.substr(1, Filename.size() - 2);
@@ -2353,27 +2376,19 @@ bool AsmParser::parseMacroArguments(cons
MCAsmMacroParameter FA;
if (Lexer.is(AsmToken::Identifier) && Lexer.peekTok().is(AsmToken::Equal)) {
- if (parseIdentifier(FA.Name)) {
- Error(IDLoc, "invalid argument identifier for formal argument");
- eatToEndOfStatement();
- return true;
- }
+ if (parseIdentifier(FA.Name))
+ return Error(IDLoc, "invalid argument identifier for formal argument");
+
+ if (Lexer.isNot(AsmToken::Equal))
+ return TokError("expected '=' after formal parameter identifier");
- if (Lexer.isNot(AsmToken::Equal)) {
- TokError("expected '=' after formal parameter identifier");
- eatToEndOfStatement();
- return true;
- }
Lex();
NamedParametersFound = true;
}
- if (NamedParametersFound && FA.Name.empty()) {
- Error(IDLoc, "cannot mix positional and keyword arguments");
- eatToEndOfStatement();
- return true;
- }
+ if (NamedParametersFound && FA.Name.empty())
+ return Error(IDLoc, "cannot mix positional and keyword arguments");
bool Vararg = HasVararg && Parameter == (NParameters - 1);
if (parseMacroArgument(FA.Value, Vararg))
@@ -2388,10 +2403,8 @@ bool AsmParser::parseMacroArguments(cons
if (FAI >= NParameters) {
assert(M && "expected macro to be defined");
- Error(IDLoc,
- "parameter named '" + FA.Name + "' does not exist for macro '" +
- M->Name + "'");
- return true;
+ return Error(IDLoc, "parameter named '" + FA.Name +
+ "' does not exist for macro '" + M->Name + "'");
}
PI = FAI;
}
@@ -2992,11 +3005,14 @@ bool AsmParser::parseDirectiveAlign(bool
if (!HasFillExpr)
FillExpr = 0;
+ // Always emit an alignment here even if we thrown an error.
+ bool ReturnVal = false;
+
// Compute alignment in bytes.
if (IsPow2) {
// FIXME: Diagnose overflow.
if (Alignment >= 32) {
- Error(AlignmentLoc, "invalid alignment value");
+ ReturnVal |= Error(AlignmentLoc, "invalid alignment value");
Alignment = 31;
}
@@ -3008,13 +3024,14 @@ bool AsmParser::parseDirectiveAlign(bool
if (Alignment == 0)
Alignment = 1;
if (!isPowerOf2_64(Alignment))
- Error(AlignmentLoc, "alignment must be a power of 2");
+ ReturnVal |= Error(AlignmentLoc, "alignment must be a power of 2");
}
// Diagnose non-sensical max bytes to align.
if (MaxBytesLoc.isValid()) {
if (MaxBytesToFill < 1) {
- Error(MaxBytesLoc, "alignment directive can never be satisfied in this "
+ ReturnVal |= Error(MaxBytesLoc,
+ "alignment directive can never be satisfied in this "
"many bytes, ignoring maximum bytes expression");
MaxBytesToFill = 0;
}
@@ -3040,7 +3057,7 @@ bool AsmParser::parseDirectiveAlign(bool
MaxBytesToFill);
}
- return false;
+ return ReturnVal;
}
/// parseDirectiveFile
@@ -3094,7 +3111,7 @@ bool AsmParser::parseDirectiveFile(SMLoc
getContext().setGenDwarfForAssembly(false);
else if (getStreamer().EmitDwarfFileDirective(FileNumber, Directory, Filename) ==
0)
- Error(FileNumberLoc, "file number already allocated");
+ return Error(FileNumberLoc, "file number already allocated");
}
return false;
@@ -3346,7 +3363,7 @@ bool AsmParser::parseDirectiveCVInlineSi
if (!getStreamer().EmitCVInlineSiteIdDirective(FunctionId, IAFunc, IAFile,
IALine, IACol, FunctionIdLoc))
- Error(FunctionIdLoc, "function id already allocated");
+ return Error(FunctionIdLoc, "function id already allocated");
return false;
}
@@ -4340,9 +4357,9 @@ bool AsmParser::parseDirectiveAbort() {
return true;
if (Str.empty())
- Error(Loc, ".abort detected. Assembly stopping.");
+ return Error(Loc, ".abort detected. Assembly stopping.");
else
- Error(Loc, ".abort '" + Str + "' detected. Assembly stopping.");
+ return Error(Loc, ".abort '" + Str + "' detected. Assembly stopping.");
// FIXME: Actually abort assembly here.
return false;
@@ -4487,11 +4504,8 @@ bool AsmParser::parseDirectiveIfc(SMLoc
bool AsmParser::parseDirectiveIfeqs(SMLoc DirectiveLoc, bool ExpectEqual) {
if (Lexer.isNot(AsmToken::String)) {
if (ExpectEqual)
- TokError("expected string parameter for '.ifeqs' directive");
- else
- TokError("expected string parameter for '.ifnes' directive");
- eatToEndOfStatement();
- return true;
+ return TokError("expected string parameter for '.ifeqs' directive");
+ return TokError("expected string parameter for '.ifnes' directive");
}
StringRef String1 = getTok().getStringContents();
@@ -4499,22 +4513,17 @@ bool AsmParser::parseDirectiveIfeqs(SMLo
if (Lexer.isNot(AsmToken::Comma)) {
if (ExpectEqual)
- TokError("expected comma after first string for '.ifeqs' directive");
- else
- TokError("expected comma after first string for '.ifnes' directive");
- eatToEndOfStatement();
- return true;
+ return TokError(
+ "expected comma after first string for '.ifeqs' directive");
+ return TokError("expected comma after first string for '.ifnes' directive");
}
Lex();
if (Lexer.isNot(AsmToken::String)) {
if (ExpectEqual)
- TokError("expected string parameter for '.ifeqs' directive");
- else
- TokError("expected string parameter for '.ifnes' directive");
- eatToEndOfStatement();
- return true;
+ return TokError("expected string parameter for '.ifeqs' directive");
+ return TokError("expected string parameter for '.ifnes' directive");
}
StringRef String2 = getTok().getStringContents();
@@ -4559,8 +4568,8 @@ bool AsmParser::parseDirectiveIfdef(SMLo
bool AsmParser::parseDirectiveElseIf(SMLoc DirectiveLoc) {
if (TheCondState.TheCond != AsmCond::IfCond &&
TheCondState.TheCond != AsmCond::ElseIfCond)
- Error(DirectiveLoc, "Encountered a .elseif that doesn't follow a .if or "
- " an .elseif");
+ return Error(DirectiveLoc, "Encountered a .elseif that doesn't follow an"
+ " .if or an .elseif");
TheCondState.TheCond = AsmCond::ElseIfCond;
bool LastIgnoreState = false;
@@ -4594,8 +4603,8 @@ bool AsmParser::parseDirectiveElse(SMLoc
if (TheCondState.TheCond != AsmCond::IfCond &&
TheCondState.TheCond != AsmCond::ElseIfCond)
- Error(DirectiveLoc, "Encountered a .else that doesn't follow a .if or an "
- ".elseif");
+ return Error(DirectiveLoc, "Encountered a .else that doesn't follow "
+ " an .if or an .elseif");
TheCondState.TheCond = AsmCond::ElseCond;
bool LastIgnoreState = false;
if (!TheCondStack.empty())
@@ -4637,18 +4646,14 @@ bool AsmParser::parseDirectiveError(SMLo
StringRef Message = ".error directive invoked in source file";
if (Lexer.isNot(AsmToken::EndOfStatement)) {
- if (Lexer.isNot(AsmToken::String)) {
- TokError(".error argument must be a string");
- eatToEndOfStatement();
- return true;
- }
+ if (Lexer.isNot(AsmToken::String))
+ return TokError(".error argument must be a string");
Message = getTok().getStringContents();
Lex();
}
- Error(L, Message);
- return true;
+ return Error(L, Message);
}
/// parseDirectiveWarning
@@ -4663,18 +4668,14 @@ bool AsmParser::parseDirectiveWarning(SM
StringRef Message = ".warning directive invoked in source file";
if (Lexer.isNot(AsmToken::EndOfStatement)) {
- if (Lexer.isNot(AsmToken::String)) {
- TokError(".warning argument must be a string");
- eatToEndOfStatement();
- return true;
- }
+ if (Lexer.isNot(AsmToken::String))
+ return TokError(".warning argument must be a string");
Message = getTok().getStringContents();
Lex();
}
- Warning(L, Message);
- return false;
+ return Warning(L, Message);
}
/// parseDirectiveEndIf
@@ -4685,8 +4686,8 @@ bool AsmParser::parseDirectiveEndIf(SMLo
return true;
if ((TheCondState.TheCond == AsmCond::NoCond) || TheCondStack.empty())
- Error(DirectiveLoc, "Encountered a .endif that doesn't follow a .if or "
- ".else");
+ return Error(DirectiveLoc, "Encountered a .endif that doesn't follow "
+ "an .if or .else");
if (!TheCondStack.empty()) {
TheCondState = TheCondStack.back();
TheCondStack.pop_back();
@@ -4838,7 +4839,7 @@ MCAsmMacro *AsmParser::parseMacroLikeBod
while (true) {
// Check whether we have reached the end of the file.
if (getLexer().is(AsmToken::Eof)) {
- Error(DirectiveLoc, "no matching '.endr' in definition");
+ printError(DirectiveLoc, "no matching '.endr' in definition");
return nullptr;
}
@@ -4855,7 +4856,8 @@ MCAsmMacro *AsmParser::parseMacroLikeBod
EndToken = getTok();
Lex();
if (Lexer.isNot(AsmToken::EndOfStatement)) {
- TokError("unexpected token in '.endr' directive");
+ printError(getTok().getLoc(),
+ "unexpected token in '.endr' directive");
return nullptr;
}
break;
@@ -4905,7 +4907,6 @@ bool AsmParser::parseDirectiveRept(SMLoc
int64_t Count;
if (!CountExpr->evaluateAsAbsolute(Count)) {
- eatToEndOfStatement();
return Error(CountLoc, "unexpected token in '" + Dir + "' directive");
}
@@ -5108,11 +5109,16 @@ bool AsmParser::parseMSInlineAsm(
continue;
ParseStatementInfo Info(&AsmStrRewrites);
- if (parseStatement(Info, &SI))
- return true;
+ bool StatementErr = parseStatement(Info, &SI);
- if (Info.ParseError)
+ if (StatementErr || Info.ParseError) {
+ // Emit pending errors if any exist.
+ printPendingErrors();
return true;
+ }
+
+ // No pending error should exist here.
+ assert(!hasPendingError() && "unexpected error from parseStatement");
if (Info.Opcode == ~0U)
continue;
@@ -5339,7 +5345,6 @@ bool parseAssignmentExpression(StringRef
if (Parser.parseExpression(Value)) {
Parser.TokError("missing expression");
- Parser.eatToEndOfStatement();
return true;
}
Modified: llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp Mon Sep 12 15:03:02 2016
@@ -12,7 +12,8 @@
using namespace llvm;
-MCAsmLexer::MCAsmLexer() : TokStart(nullptr), SkipSpace(true) {
+MCAsmLexer::MCAsmLexer()
+ : TokStart(nullptr), SkipSpace(true), IsAtStartOfStatement(true) {
CurTok.emplace_back(AsmToken::Space, StringRef());
}
Modified: llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -17,8 +17,8 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-MCAsmParser::MCAsmParser() : TargetParser(nullptr), ShowParsedOperands(0) {
-}
+MCAsmParser::MCAsmParser()
+ : TargetParser(nullptr), ShowParsedOperands(0), PendingErrors() {}
MCAsmParser::~MCAsmParser() {
}
@@ -84,8 +84,18 @@ bool MCAsmParser::check(bool P, SMLoc Lo
return false;
}
-bool MCAsmParser::TokError(const Twine &Msg, ArrayRef<SMRange> Ranges) {
- Error(getLexer().getLoc(), Msg, Ranges);
+bool MCAsmParser::TokError(const Twine &Msg, SMRange Range) {
+ return Error(getLexer().getLoc(), Msg, Range);
+}
+
+bool MCAsmParser::Error(SMLoc L, const Twine &Msg, SMRange Range) {
+ HadError = true;
+
+ MCPendingError PErr;
+ PErr.Loc = L;
+ Msg.toVector(PErr.Msg);
+ PErr.Range = Range;
+ PendingErrors.push_back(PErr);
return true;
}
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -2702,7 +2702,6 @@ bool AArch64AsmParser::parseSysAlias(Str
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
- Parser.eatToEndOfStatement();
return TokError("unexpected token in argument list");
}
@@ -3322,8 +3321,6 @@ bool AArch64AsmParser::ParseInstruction(
// IC, DC, AT, and TLBI instructions are aliases for the SYS instruction.
if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi") {
bool IsError = parseSysAlias(Head, NameLoc, Operands);
- if (IsError && getLexer().isNot(AsmToken::EndOfStatement))
- Parser.eatToEndOfStatement();
return IsError;
}
@@ -3380,7 +3377,6 @@ bool AArch64AsmParser::ParseInstruction(
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
if (parseOperand(Operands, false, false)) {
- Parser.eatToEndOfStatement();
return true;
}
@@ -3393,7 +3389,6 @@ bool AArch64AsmParser::ParseInstruction(
(N == 3 && condCodeThirdOperand) ||
(N == 2 && condCodeSecondOperand),
condCodeSecondOperand || condCodeThirdOperand)) {
- Parser.eatToEndOfStatement();
return true;
}
@@ -3425,7 +3420,6 @@ bool AArch64AsmParser::ParseInstruction(
if (getLexer().isNot(AsmToken::EndOfStatement)) {
SMLoc Loc = Parser.getTok().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
@@ -4183,8 +4177,10 @@ bool AArch64AsmParser::ParseDirective(As
if (IDVal == ".inst")
return parseDirectiveInst(Loc);
}
+ if (IDVal == MCLOHDirectiveName())
+ return parseDirectiveLOH(IDVal, Loc);
- return parseDirectiveLOH(IDVal, Loc);
+ return true;
}
static const struct {
@@ -4345,7 +4341,6 @@ bool AArch64AsmParser::parseDirectiveWor
bool AArch64AsmParser::parseDirectiveInst(SMLoc Loc) {
MCAsmParser &Parser = getParser();
if (getLexer().is(AsmToken::EndOfStatement)) {
- Parser.eatToEndOfStatement();
Error(Loc, "expected expression following directive");
return false;
}
@@ -4403,8 +4398,6 @@ bool AArch64AsmParser::parseDirectiveTLS
/// ::= .loh <lohName | lohId> label1, ..., labelN
/// The number of arguments depends on the loh identifier.
bool AArch64AsmParser::parseDirectiveLOH(StringRef IDVal, SMLoc Loc) {
- if (IDVal != MCLOHDirectiveName())
- return true;
MCLOHType Kind;
if (getParser().getTok().isNot(AsmToken::Identifier)) {
if (getParser().getTok().isNot(AsmToken::Integer))
@@ -4412,8 +4405,10 @@ bool AArch64AsmParser::parseDirectiveLOH
// We successfully get a numeric value for the identifier.
// Check if it is valid.
int64_t Id = getParser().getTok().getIntVal();
- if (Id <= -1U && !isValidMCLOHType(Id))
- return TokError("invalid numeric identifier in directive");
+ if (Id <= -1U && !isValidMCLOHType(Id)) {
+ TokError("invalid numeric identifier in directive");
+ return false;
+ }
Kind = (MCLOHType)Id;
} else {
StringRef Name = getTok().getIdentifier();
@@ -4471,25 +4466,18 @@ bool AArch64AsmParser::parseDirectiveReq
if (RegNum == static_cast<unsigned>(-1)) {
StringRef Kind;
RegNum = tryMatchVectorRegister(Kind, false);
- if (!Kind.empty()) {
- Error(SRegLoc, "vector register without type specifier expected");
- return false;
- }
+ if (!Kind.empty())
+ return Error(SRegLoc, "vector register without type specifier expected");
IsVector = true;
}
- if (RegNum == static_cast<unsigned>(-1)) {
- Parser.eatToEndOfStatement();
- Error(SRegLoc, "register name or alias expected");
- return false;
- }
+ if (RegNum == static_cast<unsigned>(-1))
+ return Error(SRegLoc, "register name or alias expected");
// Shouldn't be anything else.
- if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
- Error(Parser.getTok().getLoc(), "unexpected input in .req directive");
- Parser.eatToEndOfStatement();
- return false;
- }
+ if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+ return Error(Parser.getTok().getLoc(),
+ "unexpected input in .req directive");
Parser.Lex(); // Consume the EndOfStatement
@@ -4497,7 +4485,7 @@ bool AArch64AsmParser::parseDirectiveReq
if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
Warning(L, "ignoring redefinition of register alias '" + Name + "'");
- return true;
+ return false;
}
/// parseDirectiveUneq
@@ -4506,7 +4494,6 @@ bool AArch64AsmParser::parseDirectiveUnr
MCAsmParser &Parser = getParser();
if (Parser.getTok().isNot(AsmToken::Identifier)) {
Error(Parser.getTok().getLoc(), "unexpected input in .unreq directive.");
- Parser.eatToEndOfStatement();
return false;
}
RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -339,16 +339,14 @@ class ARMAsmParser : public MCTargetAsmP
return;
}
- void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
- return getParser().Note(L, Msg, Ranges);
+ void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ return getParser().Note(L, Msg, Range);
}
- bool Warning(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) {
- return getParser().Warning(L, Msg, Ranges);
- }
- bool Error(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None) {
- return getParser().Error(L, Msg, Ranges);
+ bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ return getParser().Warning(L, Msg, Range);
+ }
+ bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ return getParser().Error(L, Msg, Range);
}
bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
@@ -6008,7 +6006,6 @@ bool ARMAsmParser::ParseInstruction(Pars
// In Thumb1, only the branch (B) instruction can be predicated.
if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
- Parser.eatToEndOfStatement();
return Error(NameLoc, "conditional execution not supported in Thumb1");
}
@@ -6022,14 +6019,12 @@ bool ARMAsmParser::ParseInstruction(Pars
if (Mnemonic == "it") {
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
if (ITMask.size() > 3) {
- Parser.eatToEndOfStatement();
return Error(Loc, "too many conditions on IT instruction");
}
unsigned Mask = 8;
for (unsigned i = ITMask.size(); i != 0; --i) {
char pos = ITMask[i - 1];
if (pos != 't' && pos != 'e') {
- Parser.eatToEndOfStatement();
return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
}
Mask >>= 1;
@@ -6055,14 +6050,12 @@ bool ARMAsmParser::ParseInstruction(Pars
// If we had a carry-set on an instruction that can't do that, issue an
// error.
if (!CanAcceptCarrySet && CarrySetting) {
- Parser.eatToEndOfStatement();
return Error(NameLoc, "instruction '" + Mnemonic +
"' can not set flags, but 's' suffix specified");
}
// If we had a predication code on an instruction that can't do that, issue an
// error.
if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
- Parser.eatToEndOfStatement();
return Error(NameLoc, "instruction '" + Mnemonic +
"' is not predicable, but condition code specified");
}
@@ -6106,7 +6099,6 @@ bool ARMAsmParser::ParseInstruction(Pars
// For for ARM mode generate an error if the .n qualifier is used.
if (ExtraToken == ".n" && !isThumb()) {
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
- Parser.eatToEndOfStatement();
return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
"arm mode");
}
@@ -6124,7 +6116,6 @@ bool ARMAsmParser::ParseInstruction(Pars
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
if (parseOperand(Operands, Mnemonic)) {
- Parser.eatToEndOfStatement();
return true;
}
@@ -6133,16 +6124,13 @@ bool ARMAsmParser::ParseInstruction(Pars
// Parse and remember the operand.
if (parseOperand(Operands, Mnemonic)) {
- Parser.eatToEndOfStatement();
return true;
}
}
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
+ return TokError("unexpected token in argument list");
}
Parser.Lex(); // Consume the EndOfStatement
@@ -9331,7 +9319,6 @@ bool ARMAsmParser::parseLiteralValues(un
for (;;) {
const MCExpr *Value;
if (getParser().parseExpression(Value)) {
- Parser.eatToEndOfStatement();
return false;
}
@@ -9434,7 +9421,6 @@ bool ARMAsmParser::parseDirectiveThumbFu
if (getLexer().isNot(AsmToken::EndOfStatement)) {
Error(Parser.getTok().getLoc(), "unexpected token in directive");
- Parser.eatToEndOfStatement();
return false;
}
@@ -9527,14 +9513,12 @@ bool ARMAsmParser::parseDirectiveReq(Str
unsigned Reg;
SMLoc SRegLoc, ERegLoc;
if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
- Parser.eatToEndOfStatement();
Error(SRegLoc, "register name expected");
return false;
}
// Shouldn't be anything else.
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
- Parser.eatToEndOfStatement();
Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
return false;
}
@@ -9554,7 +9538,6 @@ bool ARMAsmParser::parseDirectiveReq(Str
bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
MCAsmParser &Parser = getParser();
if (Parser.getTok().isNot(AsmToken::Identifier)) {
- Parser.eatToEndOfStatement();
Error(L, "unexpected input in .unreq directive.");
return false;
}
@@ -9624,7 +9607,6 @@ bool ARMAsmParser::parseDirectiveEabiAtt
Tag = ARMBuildAttrs::AttrTypeFromString(Name);
if (Tag == -1) {
Error(TagLoc, "attribute name not recognised: " + Name);
- Parser.eatToEndOfStatement();
return false;
}
Parser.Lex();
@@ -9633,14 +9615,12 @@ bool ARMAsmParser::parseDirectiveEabiAtt
TagLoc = Parser.getTok().getLoc();
if (Parser.parseExpression(AttrExpr)) {
- Parser.eatToEndOfStatement();
return false;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
if (!CE) {
Error(TagLoc, "expected numeric constant");
- Parser.eatToEndOfStatement();
return false;
}
@@ -9649,7 +9629,6 @@ bool ARMAsmParser::parseDirectiveEabiAtt
if (Parser.getTok().isNot(AsmToken::Comma)) {
Error(Parser.getTok().getLoc(), "comma expected");
- Parser.eatToEndOfStatement();
return false;
}
Parser.Lex(); // skip comma
@@ -9676,14 +9655,12 @@ bool ARMAsmParser::parseDirectiveEabiAtt
const MCExpr *ValueExpr;
SMLoc ValueExprLoc = Parser.getTok().getLoc();
if (Parser.parseExpression(ValueExpr)) {
- Parser.eatToEndOfStatement();
return false;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
if (!CE) {
Error(ValueExprLoc, "expected numeric constant");
- Parser.eatToEndOfStatement();
return false;
}
@@ -9695,7 +9672,6 @@ bool ARMAsmParser::parseDirectiveEabiAtt
IsStringValue = false;
if (Parser.getTok().isNot(AsmToken::Comma)) {
Error(Parser.getTok().getLoc(), "comma expected");
- Parser.eatToEndOfStatement();
return false;
} else {
Parser.Lex();
@@ -9705,7 +9681,6 @@ bool ARMAsmParser::parseDirectiveEabiAtt
if (IsStringValue) {
if (Parser.getTok().isNot(AsmToken::String)) {
Error(Parser.getTok().getLoc(), "bad string constant");
- Parser.eatToEndOfStatement();
return false;
}
@@ -9849,7 +9824,6 @@ bool ARMAsmParser::parseDirectivePersona
return false;
}
if (HasExistingPersonality) {
- Parser.eatToEndOfStatement();
Error(L, "multiple personality directives");
UC.emitPersonalityLocNotes();
return false;
@@ -9857,7 +9831,6 @@ bool ARMAsmParser::parseDirectivePersona
// Parse the name of the personality routine
if (Parser.getTok().isNot(AsmToken::Identifier)) {
- Parser.eatToEndOfStatement();
Error(L, "unexpected input in .personality directive.");
return false;
}
@@ -10057,14 +10030,12 @@ bool ARMAsmParser::parseDirectiveInst(SM
Width = 4;
break;
default:
- Parser.eatToEndOfStatement();
Error(Loc, "cannot determine Thumb instruction size, "
"use inst.n/inst.w instead");
return false;
}
} else {
if (Suffix) {
- Parser.eatToEndOfStatement();
Error(Loc, "width suffixes are invalid in ARM mode");
return false;
}
@@ -10072,7 +10043,6 @@ bool ARMAsmParser::parseDirectiveInst(SM
}
if (getLexer().is(AsmToken::EndOfStatement)) {
- Parser.eatToEndOfStatement();
Error(Loc, "expected expression following directive");
return false;
}
@@ -10164,24 +10134,20 @@ bool ARMAsmParser::parseDirectivePersona
UC.recordPersonalityIndex(L);
if (!UC.hasFnStart()) {
- Parser.eatToEndOfStatement();
Error(L, ".fnstart must precede .personalityindex directive");
return false;
}
if (UC.cantUnwind()) {
- Parser.eatToEndOfStatement();
Error(L, ".personalityindex cannot be used with .cantunwind");
UC.emitCantUnwindLocNotes();
return false;
}
if (UC.hasHandlerData()) {
- Parser.eatToEndOfStatement();
Error(L, ".personalityindex must precede .handlerdata directive");
UC.emitHandlerDataLocNotes();
return false;
}
if (HasExistingPersonality) {
- Parser.eatToEndOfStatement();
Error(L, "multiple personality directives");
UC.emitPersonalityLocNotes();
return false;
@@ -10190,19 +10156,16 @@ bool ARMAsmParser::parseDirectivePersona
const MCExpr *IndexExpression;
SMLoc IndexLoc = Parser.getTok().getLoc();
if (Parser.parseExpression(IndexExpression)) {
- Parser.eatToEndOfStatement();
return false;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
if (!CE) {
- Parser.eatToEndOfStatement();
Error(IndexLoc, "index must be a constant number");
return false;
}
if (CE->getValue() < 0 ||
CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
- Parser.eatToEndOfStatement();
Error(IndexLoc, "personality routine index should be in range [0-3]");
return false;
}
@@ -10216,7 +10179,6 @@ bool ARMAsmParser::parseDirectivePersona
bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
MCAsmParser &Parser = getParser();
if (!UC.hasFnStart()) {
- Parser.eatToEndOfStatement();
Error(L, ".fnstart must precede .unwind_raw directives");
return false;
}
@@ -10228,14 +10190,12 @@ bool ARMAsmParser::parseDirectiveUnwindR
if (getLexer().is(AsmToken::EndOfStatement) ||
getParser().parseExpression(OffsetExpr)) {
Error(OffsetLoc, "expected expression");
- Parser.eatToEndOfStatement();
return false;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
if (!CE) {
Error(OffsetLoc, "offset must be a constant");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10243,7 +10203,6 @@ bool ARMAsmParser::parseDirectiveUnwindR
if (getLexer().isNot(AsmToken::Comma)) {
Error(getLexer().getLoc(), "expected comma");
- Parser.eatToEndOfStatement();
return false;
}
Parser.Lex();
@@ -10255,21 +10214,18 @@ bool ARMAsmParser::parseDirectiveUnwindR
SMLoc OpcodeLoc = getLexer().getLoc();
if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
Error(OpcodeLoc, "expected opcode expression");
- Parser.eatToEndOfStatement();
return false;
}
const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
if (!OC) {
Error(OpcodeLoc, "opcode value must be a constant");
- Parser.eatToEndOfStatement();
return false;
}
const int64_t Opcode = OC->getValue();
if (Opcode & ~0xff) {
Error(OpcodeLoc, "invalid opcode");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10280,7 +10236,6 @@ bool ARMAsmParser::parseDirectiveUnwindR
if (getLexer().isNot(AsmToken::Comma)) {
Error(getLexer().getLoc(), "unexpected token in directive");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10300,7 +10255,6 @@ bool ARMAsmParser::parseDirectiveTLSDesc
if (getLexer().isNot(AsmToken::Identifier)) {
TokError("expected variable after '.tlsdescseq' directive");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10311,7 +10265,6 @@ bool ARMAsmParser::parseDirectiveTLSDesc
if (getLexer().isNot(AsmToken::EndOfStatement)) {
Error(Parser.getTok().getLoc(), "unexpected token");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10324,12 +10277,10 @@ bool ARMAsmParser::parseDirectiveTLSDesc
bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
MCAsmParser &Parser = getParser();
if (!UC.hasFnStart()) {
- Parser.eatToEndOfStatement();
Error(L, ".fnstart must precede .movsp directives");
return false;
}
if (UC.getFPReg() != ARM::SP) {
- Parser.eatToEndOfStatement();
Error(L, "unexpected .movsp directive");
return false;
}
@@ -10337,13 +10288,11 @@ bool ARMAsmParser::parseDirectiveMovSP(S
SMLoc SPRegLoc = Parser.getTok().getLoc();
int SPReg = tryParseRegister();
if (SPReg == -1) {
- Parser.eatToEndOfStatement();
Error(SPRegLoc, "register expected");
return false;
}
if (SPReg == ARM::SP || SPReg == ARM::PC) {
- Parser.eatToEndOfStatement();
Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
return false;
}
@@ -10354,7 +10303,6 @@ bool ARMAsmParser::parseDirectiveMovSP(S
if (Parser.getTok().isNot(AsmToken::Hash)) {
Error(Parser.getTok().getLoc(), "expected #constant");
- Parser.eatToEndOfStatement();
return false;
}
Parser.Lex();
@@ -10362,14 +10310,12 @@ bool ARMAsmParser::parseDirectiveMovSP(S
const MCExpr *OffsetExpr;
SMLoc OffsetLoc = Parser.getTok().getLoc();
if (Parser.parseExpression(OffsetExpr)) {
- Parser.eatToEndOfStatement();
Error(OffsetLoc, "malformed offset expression");
return false;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
if (!CE) {
- Parser.eatToEndOfStatement();
Error(OffsetLoc, "offset must be an immediate constant");
return false;
}
@@ -10389,7 +10335,6 @@ bool ARMAsmParser::parseDirectiveObjectA
MCAsmParser &Parser = getParser();
if (getLexer().isNot(AsmToken::Identifier)) {
Error(getLexer().getLoc(), "unexpected token");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10401,7 +10346,6 @@ bool ARMAsmParser::parseDirectiveObjectA
if (ID == ARM::AK_INVALID) {
Error(ArchLoc, "unknown architecture '" + Arch + "'");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10409,7 +10353,6 @@ bool ARMAsmParser::parseDirectiveObjectA
if (getLexer().isNot(AsmToken::EndOfStatement)) {
Error(getLexer().getLoc(), "unexpected token");
- Parser.eatToEndOfStatement();
}
return false;
@@ -10442,13 +10385,11 @@ bool ARMAsmParser::parseDirectiveThumbSe
StringRef Name;
if (Parser.parseIdentifier(Name)) {
TokError("expected identifier after '.thumb_set'");
- Parser.eatToEndOfStatement();
return false;
}
if (getLexer().isNot(AsmToken::Comma)) {
TokError("expected comma after name '" + Name + "'");
- Parser.eatToEndOfStatement();
return false;
}
Lex();
@@ -10512,7 +10453,6 @@ bool ARMAsmParser::parseDirectiveArchExt
if (getLexer().isNot(AsmToken::Identifier)) {
Error(getLexer().getLoc(), "expected architecture extension name");
- Parser.eatToEndOfStatement();
return false;
}
@@ -10558,7 +10498,6 @@ bool ARMAsmParser::parseDirectiveArchExt
}
Error(ExtLoc, "unknown architectural extension: " + Name);
- Parser.eatToEndOfStatement();
return false;
}
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -114,7 +114,7 @@ class HexagonAsmParser : public MCTarget
uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
- void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
+ bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
int processInstruction(MCInst &Inst, OperandVector const &Operands,
SMLoc IDLoc);
@@ -637,60 +637,63 @@ bool HexagonAsmParser::finishBundle(SMLo
uint64_t Err = Check.getError();
if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
- Error(IDLoc,
- "unconditional branch cannot precede another branch in packet");
+ return Error(
+ IDLoc,
+ "unconditional branch cannot precede another branch in packet");
if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
- Error(IDLoc, "register `" + R +
- "' used with `.new' "
- "but not validly modified in the same packet");
+ return Error(IDLoc, "register `" + R +
+ "' used with `.new' "
+ "but not validly modified in the same packet");
if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
- Error(IDLoc, "register `" + R + "' modified more than once");
+ return Error(IDLoc, "register `" + R + "' modified more than once");
if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
- Error(IDLoc, "cannot write to read-only register `" + R + "'");
+ return Error(IDLoc, "cannot write to read-only register `" + R + "'");
if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
- Error(IDLoc, "loop-setup and some branch instructions "
- "cannot be in the same packet");
+ return Error(IDLoc, "loop-setup and some branch instructions "
+ "cannot be in the same packet");
if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
- Error(IDLoc, "packet marked with `:endloop" + N + "' " +
+ return Error(IDLoc,
+ "packet marked with `:endloop" + N + "' " +
"cannot contain instructions that modify register " +
"`" + R + "'");
}
if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
- Error(IDLoc,
- "instruction cannot appear in packet with other instructions");
+ return Error(
+ IDLoc,
+ "instruction cannot appear in packet with other instructions");
if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
- Error(IDLoc, "too many slots used in packet");
+ return Error(IDLoc, "too many slots used in packet");
if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
uint64_t Erm = Check.getShuffleError();
if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
- Error(IDLoc, "invalid instruction packet");
+ return Error(IDLoc, "invalid instruction packet");
else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
- Error(IDLoc, "invalid instruction packet: too many stores");
+ return Error(IDLoc, "invalid instruction packet: too many stores");
else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
- Error(IDLoc, "invalid instruction packet: too many loads");
+ return Error(IDLoc, "invalid instruction packet: too many loads");
else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
- Error(IDLoc, "too many branches in packet");
+ return Error(IDLoc, "too many branches in packet");
else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
- Error(IDLoc, "invalid instruction packet: out of slots");
+ return Error(IDLoc, "invalid instruction packet: out of slots");
else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
- Error(IDLoc, "invalid instruction packet: slot error");
+ return Error(IDLoc, "invalid instruction packet: slot error");
else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
- Error(IDLoc, "v60 packet violation");
+ return Error(IDLoc, "v60 packet violation");
else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
- Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
+ return Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
else
- Error(IDLoc, "unknown error in instruction packet");
+ return Error(IDLoc, "unknown error in instruction packet");
}
}
@@ -1508,7 +1511,8 @@ unsigned HexagonAsmParser::validateTarge
return Match_InvalidOperand;
}
-void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
+// FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
+bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
std::string errStr;
raw_string_ostream ES(errStr);
ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
@@ -1516,7 +1520,7 @@ void HexagonAsmParser::OutOfRange(SMLoc
ES << "0-" << Max;
else
ES << Max << "-" << (-Max - 1);
- Error(IDLoc, ES.str().c_str());
+ return Parser.printError(IDLoc, ES.str().c_str());
}
int HexagonAsmParser::processInstruction(MCInst &Inst,
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -924,9 +924,11 @@ public:
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
// FIXME: We ought to do this for -integrated-as without -via-file-asm too.
+ // FIXME: This should propagate failure up to parseStatement.
if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
- AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
- "registers");
+ AsmParser.getParser().printError(
+ StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
+ "registers");
}
void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
@@ -1860,7 +1862,7 @@ bool MipsAsmParser::processInstruction(M
if (MemOffset < -32768 || MemOffset > 32767) {
// Offset can't exceed 16bit value.
expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), true);
- return false;
+ return getParser().hasPendingError();
}
} else if (Op.isExpr()) {
const MCExpr *Expr = Op.getExpr();
@@ -1870,11 +1872,11 @@ bool MipsAsmParser::processInstruction(M
if (SR->getKind() == MCSymbolRefExpr::VK_None) {
// Expand symbol.
expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false);
- return false;
+ return getParser().hasPendingError();
}
} else if (!isEvaluated(Expr)) {
expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false);
- return false;
+ return getParser().hasPendingError();
}
}
}
@@ -2466,6 +2468,7 @@ bool MipsAsmParser::expandLoadAddress(un
Error(IDLoc, "la used to load 64-bit address");
// Continue as if we had 'dla' instead.
Is32BitAddress = false;
+ return true;
}
// dla requires 64-bit addresses.
@@ -2692,9 +2695,9 @@ bool MipsAsmParser::expandUncondBranchMM
Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
} else {
if (!isInt<17>(Offset.getImm()))
- Error(IDLoc, "branch target out of range");
+ return Error(IDLoc, "branch target out of range");
if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
- Error(IDLoc, "branch to misaligned address");
+ return Error(IDLoc, "branch to misaligned address");
Inst.clear();
Inst.setOpcode(Mips::BEQ_MM);
Inst.addOperand(MCOperand::createReg(Mips::ZERO));
@@ -3302,8 +3305,7 @@ bool MipsAsmParser::expandUlh(MCInst &In
MipsTargetStreamer &TOut = getTargetStreamer();
if (hasMips32r6() || hasMips64r6()) {
- Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
- return false;
+ return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
}
warnIfNoMacro(IDLoc);
@@ -3380,10 +3382,8 @@ bool MipsAsmParser::expandUlw(MCInst &In
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- if (hasMips32r6() || hasMips64r6()) {
- Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
- return false;
- }
+ if (hasMips32r6() || hasMips64r6())
+ return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
@@ -4817,12 +4817,10 @@ bool MipsAsmParser::parseParenSuffix(Str
Parser.Lex();
if (parseOperand(Operands, Name)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
if (Parser.getTok().isNot(AsmToken::RParen)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token, expected ')'");
}
Operands.push_back(
@@ -4847,12 +4845,10 @@ bool MipsAsmParser::parseBracketSuffix(S
Parser.Lex();
if (parseOperand(Operands, Name)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
if (Parser.getTok().isNot(AsmToken::RBrac)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token, expected ']'");
}
Operands.push_back(
@@ -4872,7 +4868,6 @@ bool MipsAsmParser::ParseInstruction(Par
// Check if we have valid mnemonic
if (!mnemonicIsValid(Name, 0)) {
- Parser.eatToEndOfStatement();
return Error(NameLoc, "unknown instruction");
}
// First operand in MCInst is instruction mnemonic.
@@ -4883,7 +4878,6 @@ bool MipsAsmParser::ParseInstruction(Par
// Read the first operand.
if (parseOperand(Operands, Name)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands))
@@ -4895,7 +4889,6 @@ bool MipsAsmParser::ParseInstruction(Par
// Parse and remember the operand.
if (parseOperand(Operands, Name)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
// Parse bracket and parenthesis suffixes before we iterate
@@ -4909,7 +4902,6 @@ bool MipsAsmParser::ParseInstruction(Par
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
Parser.Lex(); // Consume the EndOfStatement.
@@ -4919,9 +4911,7 @@ bool MipsAsmParser::ParseInstruction(Par
// FIXME: Given that these have the same name, these should both be
// consistent on affecting the Parser.
bool MipsAsmParser::reportParseError(Twine ErrorMsg) {
- MCAsmParser &Parser = getParser();
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, ErrorMsg);
}
@@ -5422,7 +5412,6 @@ bool MipsAsmParser::eatComma(StringRef E
MCAsmParser &Parser = getParser();
if (getLexer().isNot(AsmToken::Comma)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, ErrorStr);
}
@@ -5531,7 +5520,6 @@ bool MipsAsmParser::parseDirectiveCPSetu
MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
if (!FuncRegOpnd.isGPRAsmReg()) {
reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
- Parser.eatToEndOfStatement();
return false;
}
@@ -5550,7 +5538,6 @@ bool MipsAsmParser::parseDirectiveCPSetu
if (Parser.parseExpression(OffsetExpr) ||
!OffsetExpr->evaluateAsAbsolute(OffsetVal)) {
reportParseError(ExprLoc, "expected save register or stack offset");
- Parser.eatToEndOfStatement();
return false;
}
@@ -5560,7 +5547,6 @@ bool MipsAsmParser::parseDirectiveCPSetu
MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
if (!SaveOpnd.isGPRAsmReg()) {
reportParseError(SaveOpnd.getStartLoc(), "invalid register");
- Parser.eatToEndOfStatement();
return false;
}
Save = SaveOpnd.getGPR32Reg();
@@ -5848,9 +5834,8 @@ bool MipsAsmParser::parseDirectiveOption
AsmToken Tok = Parser.getTok();
// At the moment only identifiers are supported.
if (Tok.isNot(AsmToken::Identifier)) {
- Error(Parser.getTok().getLoc(), "unexpected token, expected identifier");
- Parser.eatToEndOfStatement();
- return false;
+ return Error(Parser.getTok().getLoc(),
+ "unexpected token, expected identifier");
}
StringRef Option = Tok.getIdentifier();
@@ -5862,9 +5847,8 @@ bool MipsAsmParser::parseDirectiveOption
getTargetStreamer().emitDirectiveOptionPic0();
Parser.Lex();
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
- Error(Parser.getTok().getLoc(),
- "unexpected token, expected end of statement");
- Parser.eatToEndOfStatement();
+ return Error(Parser.getTok().getLoc(),
+ "unexpected token, expected end of statement");
}
return false;
}
@@ -5876,9 +5860,8 @@ bool MipsAsmParser::parseDirectiveOption
getTargetStreamer().emitDirectiveOptionPic2();
Parser.Lex();
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
- Error(Parser.getTok().getLoc(),
- "unexpected token, expected end of statement");
- Parser.eatToEndOfStatement();
+ return Error(Parser.getTok().getLoc(),
+ "unexpected token, expected end of statement");
}
return false;
}
@@ -5969,8 +5952,7 @@ bool MipsAsmParser::parseDirectiveModule
return false; // parseDirectiveModule has finished successfully.
} else if (Option == "nooddspreg") {
if (!isABI_O32()) {
- Error(L, "'.module nooddspreg' requires the O32 ABI");
- return false;
+ return Error(L, "'.module nooddspreg' requires the O32 ABI");
}
setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
@@ -6431,8 +6413,6 @@ bool MipsAsmParser::ParseDirective(AsmTo
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
Error(Parser.getTok().getLoc(),
"unexpected token, expected end of statement");
- // Clear line
- Parser.eatToEndOfStatement();
}
return false;
}
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -84,7 +84,7 @@ class SparcAsmParser : public MCTargetAs
return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
}
- void expandSET(MCInst &Inst, SMLoc IDLoc,
+ bool expandSET(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
public:
@@ -466,7 +466,7 @@ public:
} // end namespace
-void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
+bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCOperand MCRegOp = Inst.getOperand(0);
MCOperand MCValOp = Inst.getOperand(1);
@@ -479,8 +479,8 @@ void SparcAsmParser::expandSET(MCInst &I
// Allow either a signed or unsigned 32-bit immediate.
if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
- Error(IDLoc, "set: argument must be between -2147483648 and 4294967295");
- return;
+ return Error(IDLoc,
+ "set: argument must be between -2147483648 and 4294967295");
}
// If the value was expressed as a large unsigned number, that's ok.
@@ -537,6 +537,7 @@ void SparcAsmParser::expandSET(MCInst &I
TmpInst.addOperand(MCOperand::createExpr(Expr));
Instructions.push_back(TmpInst);
}
+ return false;
}
bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
@@ -556,7 +557,8 @@ bool SparcAsmParser::MatchAndEmitInstruc
Instructions.push_back(Inst);
break;
case SP::SET:
- expandSET(Inst, IDLoc, Instructions);
+ if (expandSET(Inst, IDLoc, Instructions))
+ return true;
break;
}
@@ -626,13 +628,11 @@ bool SparcAsmParser::ParseInstruction(Pa
if (getLexer().is(AsmToken::Comma)) {
if (parseBranchModifiers(Operands) != MatchOperand_Success) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token");
}
}
if (parseOperand(Operands, Name) != MatchOperand_Success) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token");
}
@@ -645,14 +645,12 @@ bool SparcAsmParser::ParseInstruction(Pa
// Parse and remember the operand.
if (parseOperand(Operands, Name) != MatchOperand_Success) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token");
}
}
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token");
}
Parser.Lex(); // Consume the EndOfStatement.
Modified: llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -959,7 +959,6 @@ bool SystemZAsmParser::ParseInstruction(
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
if (parseOperand(Operands, Name)) {
- Parser.eatToEndOfStatement();
return true;
}
@@ -967,13 +966,11 @@ bool SystemZAsmParser::ParseInstruction(
while (getLexer().is(AsmToken::Comma)) {
Parser.Lex();
if (parseOperand(Operands, Name)) {
- Parser.eatToEndOfStatement();
return true;
}
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
return Error(Loc, "unexpected token in argument list");
}
}
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 12 15:03:02 2016
@@ -659,20 +659,14 @@ private:
}
};
- bool Error(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None,
+ bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
bool MatchingInlineAsm = false) {
MCAsmParser &Parser = getParser();
- if (MatchingInlineAsm) return true;
- return Parser.Error(L, Msg, Ranges);
- }
-
- bool ErrorAndEatStatement(SMLoc L, const Twine &Msg,
- ArrayRef<SMRange> Ranges = None,
- bool MatchingInlineAsm = false) {
- MCAsmParser &Parser = getParser();
- Parser.eatToEndOfStatement();
- return Error(L, Msg, Ranges, MatchingInlineAsm);
+ if (MatchingInlineAsm) {
+ Parser.eatToEndOfStatement();
+ return false;
+ }
+ return Parser.Error(L, Msg, Range);
}
std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
@@ -1895,13 +1889,11 @@ bool X86AsmParser::HandleAVX512Operand(O
if(getLexer().is(AsmToken::Integer)) {
// Parse memory broadcasting ({1to<NUM>}).
if (getLexer().getTok().getIntVal() != 1)
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected 1to<NUM> at this point");
+ return !TokError("Expected 1to<NUM> at this point");
Parser.Lex(); // Eat "1" of 1to8
if (!getLexer().is(AsmToken::Identifier) ||
!getLexer().getTok().getIdentifier().startswith("to"))
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected 1to<NUM> at this point");
+ return !TokError("Expected 1to<NUM> at this point");
// Recognize only reasonable suffixes.
const char *BroadcastPrimitive =
StringSwitch<const char*>(getLexer().getTok().getIdentifier())
@@ -1911,12 +1903,10 @@ bool X86AsmParser::HandleAVX512Operand(O
.Case("to16", "{1to16}")
.Default(nullptr);
if (!BroadcastPrimitive)
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Invalid memory broadcast primitive.");
+ return !TokError("Invalid memory broadcast primitive.");
Parser.Lex(); // Eat "toN" of 1toN
if (!getLexer().is(AsmToken::RCurly))
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected } at this point");
+ return !TokError("Expected } at this point");
Parser.Lex(); // Eat "}"
Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
consumedToken));
@@ -1929,8 +1919,7 @@ bool X86AsmParser::HandleAVX512Operand(O
if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
Operands.push_back(std::move(Op));
if (!getLexer().is(AsmToken::RCurly))
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected } at this point");
+ return !TokError("Expected } at this point");
Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
// Parse "zeroing non-masked" semantic {z}
@@ -1938,12 +1927,10 @@ bool X86AsmParser::HandleAVX512Operand(O
Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
if (!getLexer().is(AsmToken::Identifier) ||
getLexer().getTok().getIdentifier() != "z")
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected z at this point");
+ return !TokError("Expected z at this point");
Parser.Lex(); // Eat the z
if (!getLexer().is(AsmToken::RCurly))
- return !ErrorAndEatStatement(getLexer().getLoc(),
- "Expected } at this point");
+ return !TokError("Expected } at this point");
Parser.Lex(); // Eat the }
}
}
@@ -2287,7 +2274,6 @@ bool X86AsmParser::ParseInstruction(Pars
if (!HandleAVX512Operand(Operands, *Operands.back()))
return true;
} else {
- Parser.eatToEndOfStatement();
return true;
}
// check for comma and eat it
@@ -2303,8 +2289,7 @@ bool X86AsmParser::ParseInstruction(Pars
isParsingIntelSyntax() && isParsingInlineAsm() &&
(getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
- return ErrorAndEatStatement(getLexer().getLoc(),
- "unexpected token in argument list");
+ return TokError("unexpected token in argument list");
}
// Consume the EndOfStatement or the prefix separator Slash
@@ -2570,7 +2555,6 @@ void X86AsmParser::MatchFPUWaitAlias(SML
bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
bool MatchingInlineAsm) {
assert(ErrorInfo && "Unknown missing feature!");
- ArrayRef<SMRange> EmptyRanges = None;
SmallString<126> Msg;
raw_svector_ostream OS(Msg);
OS << "instruction requires:";
@@ -2580,7 +2564,7 @@ bool X86AsmParser::ErrorMissingFeature(S
OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
Mask <<= 1;
}
- return Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
+ return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
}
bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
@@ -2591,7 +2575,7 @@ bool X86AsmParser::MatchAndEmitATTInstru
assert(!Operands.empty() && "Unexpect empty operand list!");
X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
assert(Op.isToken() && "Leading operand should always be a mnemonic!");
- ArrayRef<SMRange> EmptyRanges = None;
+ SMRange EmptyRange = None;
// First, handle aliases that expand to multiple instructions.
MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
@@ -2698,7 +2682,7 @@ bool X86AsmParser::MatchAndEmitATTInstru
OS << "'" << Base << MatchChars[i] << "'";
}
OS << ")";
- Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
+ Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
return true;
}
@@ -2708,17 +2692,15 @@ bool X86AsmParser::MatchAndEmitATTInstru
// mnemonic was invalid.
if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
if (!WasOriginallyInvalidOperand) {
- SMRange OpRange = Op.getLocRange();
- ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges : OpRange;
return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
- Ranges, MatchingInlineAsm);
+ Op.getLocRange(), MatchingInlineAsm);
}
// Recover location info for the operand if we know which was the problem.
if (ErrorInfo != ~0ULL) {
if (ErrorInfo >= Operands.size())
- return Error(IDLoc, "too few operands for instruction",
- EmptyRanges, MatchingInlineAsm);
+ return Error(IDLoc, "too few operands for instruction", EmptyRange,
+ MatchingInlineAsm);
X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
if (Operand.getStartLoc().isValid()) {
@@ -2728,7 +2710,7 @@ bool X86AsmParser::MatchAndEmitATTInstru
}
}
- return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+ return Error(IDLoc, "invalid operand for instruction", EmptyRange,
MatchingInlineAsm);
}
@@ -2745,13 +2727,13 @@ bool X86AsmParser::MatchAndEmitATTInstru
// operand failure.
if (std::count(std::begin(Match), std::end(Match),
Match_InvalidOperand) == 1) {
- return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+ return Error(IDLoc, "invalid operand for instruction", EmptyRange,
MatchingInlineAsm);
}
// If all of these were an outright failure, report it in a useless way.
Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
- EmptyRanges, MatchingInlineAsm);
+ EmptyRange, MatchingInlineAsm);
return true;
}
@@ -2764,7 +2746,7 @@ bool X86AsmParser::MatchAndEmitIntelInst
X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
assert(Op.isToken() && "Leading operand should always be a mnemonic!");
StringRef Mnemonic = Op.getToken();
- ArrayRef<SMRange> EmptyRanges = None;
+ SMRange EmptyRange = None;
// First, handle aliases that expand to multiple instructions.
MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
@@ -2836,10 +2818,8 @@ bool X86AsmParser::MatchAndEmitIntelInst
// If it's a bad mnemonic, all results will be the same.
if (Match.back() == Match_MnemonicFail) {
- ArrayRef<SMRange> Ranges =
- MatchingInlineAsm ? EmptyRanges : Op.getLocRange();
return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
- Ranges, MatchingInlineAsm);
+ Op.getLocRange(), MatchingInlineAsm);
}
// If exactly one matched, then we treat that as a successful match (and the
@@ -2862,11 +2842,9 @@ bool X86AsmParser::MatchAndEmitIntelInst
} else if (NumSuccessfulMatches > 1) {
assert(UnsizedMemOp &&
"multiple matches only possible with unsized memory operands");
- SMRange OpRange = UnsizedMemOp->getLocRange();
- ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges : OpRange;
return Error(UnsizedMemOp->getStartLoc(),
"ambiguous operand size for instruction '" + Mnemonic + "\'",
- Ranges, MatchingInlineAsm);
+ UnsizedMemOp->getLocRange(), MatchingInlineAsm);
}
// If one instruction matched with a missing feature, report this as a
@@ -2882,12 +2860,12 @@ bool X86AsmParser::MatchAndEmitIntelInst
// operand failure.
if (std::count(std::begin(Match), std::end(Match),
Match_InvalidOperand) == 1) {
- return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+ return Error(IDLoc, "invalid operand for instruction", EmptyRange,
MatchingInlineAsm);
}
// If all of these were an outright failure, report it in a useless way.
- return Error(IDLoc, "unknown instruction mnemonic", EmptyRanges,
+ return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
MatchingInlineAsm);
}
Modified: llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s Mon Sep 12 15:03:02 2016
@@ -21,47 +21,21 @@
// CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
sqrdmlah v0.2s, v1.4h, v2.8h
+// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
sqrdmlsh v0.4s, v1.8h, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlah v0.2s, v1.4h, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: sqrdmlsh v0.4s, v1.8h, v2.2s
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
//AdvSIMD RDMA scalar
sqrdmlah h0, h1, h2
Modified: llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s (original)
+++ llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s Mon Sep 12 15:03:02 2016
@@ -17,3 +17,5 @@ diagnostics:
.inst 0x5e104020 0x5e104020
// CHECK-ERROR: unexpected token in directive
+
+// CHECK-ERROR-NOT: unexpected token at start of statement
Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=281249&r1=281248&r2=281249&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Mon Sep 12 15:03:02 2016
@@ -1343,7 +1343,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ushll v1.16b, v25.16b, #6
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: sshll2 v0.2d, v3.8s, #15
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -2114,13 +2114,13 @@
saddl2 v0.8h, v1.16h, v2.16b
saddl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: saddl2 v0.4s, v1.8s, v2.8h
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: saddl2 v0.8h, v1.16h, v2.16b
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: saddl2 v0.2d, v1.4d, v2.4s
// CHECK-ERROR: ^
@@ -2142,23 +2142,19 @@
uaddl2 v0.4s, v1.8s, v2.8h
uaddl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uaddl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uaddl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uaddl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT: uaddl2 v0.8h, v1.16h, v2.16b
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT: uaddl2 v0.4s, v1.8s, v2.8h
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT: uaddl2 v0.2d, v1.4d, v2.4s
ssubl v0.8h, v1.8h, v2.8b
ssubl v0.4s, v1.4s, v2.4h
ssubl v0.2d, v1.2d, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: ssubl v0.8h, v1.8h, v2.8b
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
+// CHECK-ERROR-NEXT: ssubl v0.8h, v1.8h, v2.8b
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ssubl v0.4s, v1.4s, v2.4h
// CHECK-ERROR: ^
@@ -2170,13 +2166,13 @@
ssubl2 v0.4s, v1.8s, v2.8h
ssubl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: ssubl2 v0.8h, v1.16h, v2.16b
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: ssubl2 v0.4s, v1.8s, v2.8h
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: ssubl2 v0.2d, v1.4d, v2.4s
// CHECK-ERROR: ^
@@ -2198,15 +2194,12 @@
usubl2 v0.4s, v1.8s, v2.8h
usubl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: usubl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: usubl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: usubl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
sabal v0.8h, v1.8h, v2.8b
sabal v0.4s, v1.4s, v2.4h
@@ -2226,13 +2219,13 @@
sabal2 v0.4s, v1.8s, v2.8h
sabal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: sabal2 v0.8h, v1.16h, v2.16b
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: sabal2 v0.4s, v1.8s, v2.8h
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: sabal2 v0.2d, v1.4d, v2.4s
// CHECK-ERROR: ^
@@ -2254,15 +2247,12 @@
uabal2 v0.4s, v1.8s, v2.8h
uabal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
sabdl v0.8h, v1.8h, v2.8b
sabdl v0.4s, v1.4s, v2.4h
@@ -2282,15 +2272,12 @@
sabdl2 v0.4s, v1.8s, v2.8h
sabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: sabdl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: sabdl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: sabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
uabdl v0.8h, v1.8h, v2.8b
uabdl v0.4s, v1.4s, v2.4h
@@ -2310,15 +2297,12 @@
uabdl2 v0.4s, v1.8s, v2.8h
uabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabdl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabdl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: uabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
smlal v0.8h, v1.8h, v2.8b
smlal v0.4s, v1.4s, v2.4h
@@ -2338,71 +2322,56 @@
smlal2 v0.4s, v1.8s, v2.8h
smlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
umlal v0.8h, v1.8h, v2.8b
umlal v0.4s, v1.4s, v2.4h
umlal v0.2d, v1.2d, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
// CHECK-ERROR: umlal v0.8h, v1.8h, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:22: error: invalid operand for instruction
// CHECK-ERROR: umlal v0.4s, v1.4s, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:22: error: invalid operand for instruction
// CHECK-ERROR: umlal v0.2d, v1.2d, v2.2s
-// CHECK-ERROR: ^
umlal2 v0.8h, v1.16h, v2.16b
umlal2 v0.4s, v1.8s, v2.8h
umlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
smlsl v0.8h, v1.8h, v2.8b
smlsl v0.4s, v1.4s, v2.4h
smlsl v0.2d, v1.2d, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
// CHECK-ERROR: smlsl v0.8h, v1.8h, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:22: error: invalid operand for instruction
// CHECK-ERROR: smlsl v0.4s, v1.4s, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:22: error: invalid operand for instruction
// CHECK-ERROR: smlsl v0.2d, v1.2d, v2.2s
-// CHECK-ERROR: ^
smlsl2 v0.8h, v1.16h, v2.16b
smlsl2 v0.4s, v1.8s, v2.8h
smlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlsl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
umlsl v0.8h, v1.8h, v2.8b
umlsl v0.4s, v1.4s, v2.4h
@@ -2422,15 +2391,12 @@
umlsl2 v0.4s, v1.8s, v2.8h
umlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlsl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
smull v0.8h, v1.8h, v2.8b
smull v0.4s, v1.4s, v2.4h
@@ -2450,15 +2416,12 @@
smull2 v0.4s, v1.8s, v2.8h
smull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: smull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
umull v0.8h, v1.8h, v2.8b
umull v0.4s, v1.4s, v2.4h
@@ -2478,15 +2441,12 @@
umull2 v0.4s, v1.8s, v2.8h
umull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: umull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
//------------------------------------------------------------------------------
// Long - Variant 2
@@ -2505,12 +2465,10 @@
sqdmlal2 v0.4s, v1.8s, v2.8h
sqdmlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
// Mismatched vector types
sqdmlal v0.8h, v1.8b, v2.8b
@@ -2536,12 +2494,10 @@
sqdmlsl2 v0.4s, v1.8s, v2.8h
sqdmlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
// Mismatched vector types
sqdmlsl v0.8h, v1.8b, v2.8b
@@ -2568,12 +2524,10 @@
sqdmull2 v0.4s, v1.8s, v2.8h
sqdmull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
// CHECK-ERROR: sqdmull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR: ^
// Mismatched vector types
sqdmull v0.8h, v1.8b, v2.8b
@@ -2616,16 +2570,12 @@
pmull2 v0.8h, v1.16h, v2.16b
-
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-1]]:23: error: invalid vector kind qualifier
// CHECK-ERROR: pmull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR: ^
pmull2 v0.q, v1.2d, v2.2d
-
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-1]]:16: error: invalid vector kind qualifier
// CHECK-ERROR: pmull2 v0.q, v1.2d, v2.2d
-// CHECK-ERROR: ^
// Mismatched vector types
pmull2 v0.4s, v1.8h v2.8h
@@ -2662,15 +2612,12 @@
saddw2 v0.4s, v1.4s, v2.8s
saddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: saddw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: saddw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: saddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: ^
uaddw v0.8h, v1.8h, v2.8h
uaddw v0.4s, v1.4s, v2.4s
@@ -2690,15 +2637,12 @@
uaddw2 v0.4s, v1.4s, v2.8s
uaddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: uaddw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: uaddw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: uaddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: ^
ssubw v0.8h, v1.8h, v2.8h
ssubw v0.4s, v1.4s, v2.4s
@@ -2718,15 +2662,12 @@
ssubw2 v0.4s, v1.4s, v2.8s
ssubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: ssubw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: ssubw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: ssubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: ^
usubw v0.8h, v1.8h, v2.8h
usubw v0.4s, v1.4s, v2.4s
@@ -2746,15 +2687,12 @@
usubw2 v0.4s, v1.4s, v2.8s
usubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: usubw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: usubw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
// CHECK-ERROR: usubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR: ^
//------------------------------------------------------------------------------
// Narrow
@@ -2764,15 +2702,12 @@
addhn v0.4h, v1.4s, v2.4h
addhn v0.2s, v1.2d, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:29: error: invalid vector kind qualifier
// CHECK-ERROR: addhn v0.8b, v1.8h, v2.8d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:29: error: invalid operand for instruction
// CHECK-ERROR: addhn v0.4h, v1.4s, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:29: error: invalid operand for instruction
// CHECK-ERROR: addhn v0.2s, v1.2d, v2.2s
-// CHECK-ERROR: ^
addhn2 v0.16b, v1.8h, v2.8b
addhn2 v0.8h, v1.4s, v2.4h
@@ -4479,10 +4414,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: dup v1.16b, d2
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: dup v11.8s, w16
// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: dup v17.4d, w28
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -6458,416 +6393,257 @@
//----------------------------------------------------------------------
uzp1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
uzp1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
uzp2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
uzp2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
zip1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
zip1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
+\
zip2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
zip2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
trn1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
trn1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
trn2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
trn2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
//----------------------------------------------------------------------
// Permutation with 3 vectors
//----------------------------------------------------------------------
uzp1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
uzp1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp1 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
uzp2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
uzp2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
uzp2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
uzp2 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: uzp2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
zip1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
zip1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
+
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
zip2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
zip2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
zip2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
zip2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: zip2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
trn1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
trn1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
trn2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
trn2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
trn2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
trn2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: trn2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Floating Point multiply (scalar, by element)
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