[PATCH] D24396: Target Power9 bit counting and vector comparison instructions through builtins (backend portion)

[Nemanja Ivanovic via llvm-commits]

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This patch adds support for the "vector count trailing zeroes", "vector compare not equal" and "vector compare not equal or zero instructions" as well as "scalar count trailing zeroes" instructions. It also changes the vector negation to use XXLNOR (when VSX is enabled) so as not to increase register pressure (previously this was done with a splat immediate of all ones followed by an XXLXOR). This was done because the altivec.h builtins (patch to follow) use vector negation and the use of an additional register for the splat immediate is not optimal.

Repository:
  rL LLVM

https://reviews.llvm.org/D24396

Files:
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrAltivec.td
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll
  test/CodeGen/PowerPC/vsx.ll

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