[llvm] r280927 - [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDemandedBits
Mikael Holmén via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 9 01:10:08 PDT 2016
Hi Simon,
With this commit the attached program crashes in SelectionDAG.cpp:
bin/llc -march=x86-64 -mcpu=corei7 -tail-dup-verify -verify-coalescing
-verify-dom-info -verify-loop-info -o /dev/null reduced.ll
llc: ../lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1013: llvm::SDValue
llvm::SelectionDAG::getZeroExtendInReg(llvm::SDValue, const llvm::SDLoc
&, llvm::EVT): Assertion `!VT.isVector() && "getZeroExtendInReg should
use the vector element type instead of " "the vector type!"' failed.
#0 0x00000000026a2ebf llvm::sys::PrintStackTrace(llvm::raw_ostream&)
/data/repo/llvm-patch/build-all-Debug/../lib/Support/Unix/Signals.inc:402:5
#1 0x00000000026a33c9 PrintStackTraceSignalHandler(void*)
/data/repo/llvm-patch/build-all-Debug/../lib/Support/Unix/Signals.inc:466:1
#2 0x00000000026a1a43 llvm::sys::RunSignalHandlers()
/data/repo/llvm-patch/build-all-Debug/../lib/Support/Signals.cpp:45:5
#3 0x00000000026a3a0e SignalHandler(int)
/data/repo/llvm-patch/build-all-Debug/../lib/Support/Unix/Signals.inc:256:1
#4 0x00007f78b3181330 __restore_rt
(/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)
#5 0x00007f78b1d74c37 gsignal
/build/eglibc-oGUzwX/eglibc-2.19/signal/../nptl/sysdeps/unix/sysv/linux/raise.c:56:0
#6 0x00007f78b1d78028 abort
/build/eglibc-oGUzwX/eglibc-2.19/stdlib/abort.c:91:0
#7 0x00007f78b1d6dbf6 __assert_fail_base
/build/eglibc-oGUzwX/eglibc-2.19/assert/assert.c:92:0
#8 0x00007f78b1d6dca2 (/lib/x86_64-linux-gnu/libc.so.6+0x2fca2)
#9 0x00000000024aacba
llvm::SelectionDAG::getZeroExtendInReg(llvm::SDValue, llvm::SDLoc
const&, llvm::EVT)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1011:3
#10 0x0000000002361fe8 (anonymous
namespace)::DAGCombiner::visitSIGN_EXTEND_INREG(llvm::SDNode*)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7030:12
#11 0x000000000233a67e (anonymous
namespace)::DAGCombiner::visit(llvm::SDNode*)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1408:40
#12 0x0000000002339cfb (anonymous
namespace)::DAGCombiner::combine(llvm::SDNode*)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1459:16
#13 0x00000000023395f9 (anonymous
namespace)::DAGCombiner::Run(llvm::CombineLevel)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1313:18
#14 0x0000000002339072 llvm::SelectionDAG::Combine(llvm::CombineLevel,
llvm::AAResults&, llvm::CodeGenOpt::Level)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/DAGCombiner.cpp:15183:3
#15 0x00000000024f5b7f llvm::SelectionDAGISel::CodeGenAndEmitDAG()
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:789:7
#16 0x00000000024f536e
llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction
const, false>, llvm::ilist_iterator<llvm::Instruction const, false>,
bool&)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:684:1
#17 0x00000000024f51bb
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1489:5
#18 0x00000000024f2ffc
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:509:36
#19 0x000000000166ee9b (anonymous
namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
/data/repo/llvm-patch/build-all-Debug/../lib/Target/X86/X86ISelDAGToDAG.cpp:175:25
#20 0x0000000001d17ed0
llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
/data/repo/llvm-patch/build-all-Debug/../lib/CodeGen/MachineFunctionPass.cpp:62:8
#21 0x00000000020e2d8d
llvm::FPPassManager::runOnFunction(llvm::Function&)
/data/repo/llvm-patch/build-all-Debug/../lib/IR/LegacyPassManager.cpp:1522:23
#22 0x00000000020e30c5 llvm::FPPassManager::runOnModule(llvm::Module&)
/data/repo/llvm-patch/build-all-Debug/../lib/IR/LegacyPassManager.cpp:1543:16
#23 0x00000000020e38ae (anonymous
namespace)::MPPassManager::runOnModule(llvm::Module&)
/data/repo/llvm-patch/build-all-Debug/../lib/IR/LegacyPassManager.cpp:1599:23
#24 0x00000000020e33ab llvm::legacy::PassManagerImpl::run(llvm::Module&)
/data/repo/llvm-patch/build-all-Debug/../lib/IR/LegacyPassManager.cpp:1702:16
#25 0x00000000020e3df1 llvm::legacy::PassManager::run(llvm::Module&)
/data/repo/llvm-patch/build-all-Debug/../lib/IR/LegacyPassManager.cpp:1733:3
#26 0x00000000008a5fbe compileModule(char**, llvm::LLVMContext&)
/data/repo/llvm-patch/build-all-Debug/../tools/llc/llc.cpp:509:42
#27 0x00000000008a465a main
/data/repo/llvm-patch/build-all-Debug/../tools/llc/llc.cpp:274:13
#28 0x00007f78b1d5ff45 __libc_start_main
/build/eglibc-oGUzwX/eglibc-2.19/csu/libc-start.c:321:0
#29 0x00000000008a4204 _start (build-all-Debug/bin/llc+0x8a4204)
when I do
llc -march=x86-64 -mcpu=corei7 -o /dev/null reduced.ll
The input is generated by llvm-stress and then bugpoint reduced.
Regards,
Mikael
On 09/08/2016 02:57 PM, Simon Pilgrim via llvm-commits wrote:
> Author: rksimon
> Date: Thu Sep 8 07:57:51 2016
> New Revision: 280927
>
> URL: http://llvm.org/viewvc/llvm-project?rev=280927&view=rev
> Log:
> [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDemandedBits
>
> Add the ability to computeKnownBits and SimplifyDemandedBits to extract the known zero/one bits from BUILD_VECTOR, returning the known bits that are shared by every vector element.
>
> This is an initial step towards determining the sign bits of a vector (PR29079).
>
> Differential Revision: https://reviews.llvm.org/D24253
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll
> llvm/trunk/test/CodeGen/AMDGPU/load-global-i16.ll
> llvm/trunk/test/CodeGen/X86/combine-and.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=280927&r1=280926&r2=280927&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Sep 8 07:57:51 2016
> @@ -2016,6 +2016,26 @@ void SelectionDAG::computeKnownBits(SDVa
> KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
> KnownZero = ~KnownOne;
> break;
> + case ISD::BUILD_VECTOR:
> + // Collect the known bits that are shared by every vector element.
> + KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
> + for (SDValue SrcOp : Op->ops()) {
> + computeKnownBits(SrcOp, KnownZero2, KnownOne2, Depth + 1);
> +
> + // BUILD_VECTOR can implicitly truncate sources, we must handle this.
> + if (SrcOp.getValueSizeInBits() != BitWidth) {
> + assert(SrcOp.getValueSizeInBits() > BitWidth &&
> + "Expected BUILD_VECTOR implicit truncation");
> + KnownOne2 = KnownOne2.trunc(BitWidth);
> + KnownZero2 = KnownZero2.trunc(BitWidth);
> + }
> +
> + // Known bits are the values that are shared by every element.
> + // TODO: support per-element known bits.
> + KnownOne &= KnownOne2;
> + KnownZero &= KnownZero2;
> + }
> + break;
> case ISD::AND:
> // If either the LHS or the RHS are Zero, the result is zero.
> computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=280927&r1=280926&r2=280927&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Sep 8 07:57:51 2016
> @@ -468,6 +468,33 @@ bool TargetLowering::SimplifyDemandedBit
> KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
> KnownZero = ~KnownOne;
> return false; // Don't fall through, will infinitely loop.
> + case ISD::BUILD_VECTOR:
> + // Collect the known bits that are shared by every constant vector element.
> + KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
> + for (SDValue SrcOp : Op->ops()) {
> + if (!isa<ConstantSDNode>(SrcOp)) {
> + // We can only handle all constant values - bail out with no known bits.
> + KnownZero = KnownOne = APInt(BitWidth, 0);
> + return false;
> + }
> + KnownOne2 = cast<ConstantSDNode>(SrcOp)->getAPIntValue();
> + KnownZero2 = ~KnownOne2;
> +
> + // BUILD_VECTOR can implicitly truncate sources, we must handle this.
> + if (KnownOne2.getBitWidth() != BitWidth) {
> + assert(KnownOne2.getBitWidth() > BitWidth &&
> + KnownZero2.getBitWidth() > BitWidth &&
> + "Expected BUILD_VECTOR implicit truncation");
> + KnownOne2 = KnownOne2.trunc(BitWidth);
> + KnownZero2 = KnownZero2.trunc(BitWidth);
> + }
> +
> + // Known bits are the values that are shared by every element.
> + // TODO: support per-element known bits.
> + KnownOne &= KnownOne2;
> + KnownZero &= KnownZero2;
> + }
> + return false; // Don't fall through, will infinitely loop.
> case ISD::AND:
> // If the RHS is a constant, check to see if the LHS would be zero without
> // using the bits from the RHS. Below, we use knowledge about the RHS to
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll?rev=280927&r1=280926&r2=280927&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll Thu Sep 8 07:57:51 2016
> @@ -138,7 +138,7 @@ define void @constant_sextload_v1i16_to_
> ; v2i16 is naturally 4 byte aligned
> ; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
> ; TODO: This should use DST, but for some there are redundant MOVs
> -; EG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> +; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> ; EG: 16
> define void @constant_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 {
> %load = load <2 x i16>, <2 x i16> addrspace(2)* %in
> @@ -212,9 +212,10 @@ entry:
> ; v4i16 is naturally 8 byte aligned
> ; EG: VTX_READ_64 [[DST:T[0-9]\.XY]], {{T[0-9].[XYZW]}}, 0, #1
> ; TODO: These should use DST, but for some there are redundant MOVs
> -; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> -; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> +; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> ; EG-DAG: 16
> +; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> +; EG-DAG: AND_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> ; EG-DAG: 16
> define void @constant_constant_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 {
> %load = load <4 x i16>, <4 x i16> addrspace(2)* %in
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/load-global-i16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-global-i16.ll?rev=280927&r1=280926&r2=280927&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/load-global-i16.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/load-global-i16.ll Thu Sep 8 07:57:51 2016
> @@ -147,7 +147,7 @@ define void @global_sextload_v1i16_to_v1
>
> ; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
> ; TODO: This should use DST, but for some there are redundant MOVs
> -; EG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> +; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> ; EG: 16
> define void @global_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
> %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
> @@ -219,9 +219,10 @@ entry:
>
> ; EG: VTX_READ_64 [[DST:T[0-9]\.XY]], {{T[0-9].[XYZW]}}, 0, #1
> ; TODO: These should use DST, but for some there are redundant MOVs
> -; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal
> -; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> +; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> ; EG-DAG: 16
> +; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> +; EG-DAG: AND_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal
> ; EG-DAG: 16
> define void @global_global_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
> %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
>
> Modified: llvm/trunk/test/CodeGen/X86/combine-and.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-and.ll?rev=280927&r1=280926&r2=280927&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/combine-and.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/combine-and.ll Thu Sep 8 07:57:51 2016
> @@ -210,10 +210,7 @@ define <4 x i32> @and_or_v4i32(<4 x i32>
> define <2 x i64> @and_or_zext_v2i32(<2 x i32> %a0) {
> ; CHECK-LABEL: and_or_zext_v2i32:
> ; CHECK: # BB#0:
> -; CHECK-NEXT: pxor %xmm1, %xmm1
> -; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
> -; CHECK-NEXT: por {{.*}}(%rip), %xmm0
> -; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
> +; CHECK-NEXT: xorps %xmm0, %xmm0
> ; CHECK-NEXT: retq
> %1 = zext <2 x i32> %a0 to <2 x i64>
> %2 = or <2 x i64> %1, <i64 1, i64 1>
> @@ -224,10 +221,7 @@ define <2 x i64> @and_or_zext_v2i32(<2 x
> define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) {
> ; CHECK-LABEL: and_or_zext_v4i16:
> ; CHECK: # BB#0:
> -; CHECK-NEXT: pxor %xmm1, %xmm1
> -; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
> -; CHECK-NEXT: por {{.*}}(%rip), %xmm0
> -; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
> +; CHECK-NEXT: xorps %xmm0, %xmm0
> ; CHECK-NEXT: retq
> %1 = zext <4 x i16> %a0 to <4 x i32>
> %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
>
>
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-------------- next part --------------
; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "bugpoint-output-e6eee0b.bc"
target triple = "x86_64-unknown-linux-gnu"
define void @autogen_SD16953(i8*) {
BB:
%L5 = load i8, i8* %0
%Sl9 = select i1 true, i8 %L5, i8 undef
%B21 = udiv i8 %Sl9, -93
br label %CF
CF: ; preds = %CF246, %BB
%I40 = insertelement <4 x i8> zeroinitializer, i8 %B21, i32 1
%B41 = srem <4 x i8> %I40, %I40
br label %CF237
CF237: ; preds = %CF237, %CF
%Cmp73 = icmp ne i1 undef, undef
br i1 %Cmp73, label %CF237, label %CF246
CF246: ; preds = %CF237
%Cmp117 = icmp ult <4 x i8> %B41, undef
%E156 = extractelement <4 x i1> %Cmp117, i32 2
br label %CF
}
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