[llvm] r280798 - [mips] Disable the TImode shift libcalls for 32-bit targets.

[Vasileios Kalintiris via llvm-commits]

Author: vkalintiris
Date: Wed Sep  7 05:01:18 2016
New Revision: 280798

URL: http://llvm.org/viewvc/llvm-project?rev=280798&view=rev
Log:
[mips] Disable the TImode shift libcalls for 32-bit targets.

Summary:
The o32 ABI doesn't not support the TImode helpers. For the time being,
disable just the shift libcalls as they break recursive builds on MIPS.

Reviewers: sdardis

Subscribers: llvm-commits, sdardis

Differential Revision: https://reviews.llvm.org/D24259

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
    llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
    llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=280798&r1=280797&r2=280798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Sep  7 05:01:18 2016
@@ -426,6 +426,13 @@ MipsTargetLowering::MipsTargetLowering(c
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::AssertZext);
 
+  if (ABI.IsO32()) {
+    // These libcalls are not available in 32-bit.
+    setLibcallName(RTLIB::SHL_I128, nullptr);
+    setLibcallName(RTLIB::SRL_I128, nullptr);
+    setLibcallName(RTLIB::SRA_I128, nullptr);
+  }
+
   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=280798&r1=280797&r2=280798&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll Wed Sep  7 05:01:18 2016
@@ -162,7 +162,9 @@ define signext i128 @ashr_i128(i128 sign
 entry:
 ; ALL-LABEL: ashr_i128:
 
-  ; GP32:           lw        $25, %call16(__ashrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
@@ -213,8 +215,6 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
-  ; MM:             lw        $25, %call16(__ashrti3)($2)
-
   %r = ashr i128 %a, %b
   ret i128 %r
 }

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=280798&r1=280797&r2=280798&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll Wed Sep  7 05:01:18 2016
@@ -153,7 +153,9 @@ define signext i128 @lshr_i128(i128 sign
 entry:
 ; ALL-LABEL: lshr_i128:
 
-  ; GP32:         lw      $25, %call16(__lshrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
@@ -200,8 +202,6 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__lshrti3)($2)
-
   %r = lshr i128 %a, %b
   ret i128 %r
 }

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll?rev=280798&r1=280797&r2=280798&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll Wed Sep  7 05:01:18 2016
@@ -169,7 +169,9 @@ define signext i128 @shl_i128(i128 signe
 entry:
 ; ALL-LABEL: shl_i128:
 
-  ; GP32:           lw        $25, %call16(__ashlti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashlti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashlti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
@@ -216,8 +218,6 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__ashlti3)($2)
-
   %r = shl i128 %a, %b
   ret i128 %r
 }