[PATCH] D24288: Don't reduce mul if the target doesn't support SSE2

[Wei Mi via llvm-commits]

wmi created this revision.
wmi added reviewers: eli.friedman, mkuper.
wmi added a subscriber: llvm-commits.
wmi set the repository for this revision to rL LLVM.

The patch is to fix https://llvm.org/bugs/show_bug.cgi?id=30298, which is caused by https://reviews.llvm.org/D20931

pmullw/pmulhw/punpcklwd/punpckhwd are not supported in SSE, so I add a bail out if the target has no SSE2. 

Repository:
  rL LLVM

https://reviews.llvm.org/D24288

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/pr30298.ll

Index: test/CodeGen/X86/pr30298.ll
===================================================================
--- test/CodeGen/X86/pr30298.ll
+++ test/CodeGen/X86/pr30298.ll
@@ -0,0 +1,22 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=i386-pc-linux-gnu -mattr=+sse < %s | FileCheck %s
+; CHECK-NOT: pmullw
+ at c = external global i32*, align 8
+
+define void @mul_2xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64 %index) {
+entry:
+  %pre = load i32*, i32** @c
+  %tmp6 = getelementptr inbounds i8, i8* %a, i64 %index
+  %tmp7 = bitcast i8* %tmp6 to <2 x i8>*
+  %wide.load = load <2 x i8>, <2 x i8>* %tmp7, align 1
+  %tmp8 = zext <2 x i8> %wide.load to <2 x i32>
+  %tmp10 = getelementptr inbounds i8, i8* %b, i64 %index
+  %tmp11 = bitcast i8* %tmp10 to <2 x i8>*
+  %wide.load17 = load <2 x i8>, <2 x i8>* %tmp11, align 1
+  %tmp12 = zext <2 x i8> %wide.load17 to <2 x i32>
+  %tmp13 = mul nuw nsw <2 x i32> %tmp12, %tmp8
+  %tmp14 = getelementptr inbounds i32, i32* %pre, i64 %index
+  %tmp15 = bitcast i32* %tmp14 to <2 x i32>*
+  store <2 x i32> %tmp13, <2 x i32>* %tmp15, align 4
+  ret void
+}
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -27854,7 +27854,8 @@
                                const X86Subtarget &Subtarget) {
   // pmulld is supported since SSE41. It is better to use pmulld
   // instead of pmullw+pmulhw.
-  if (Subtarget.hasSSE41())
+  // pmullw/pmulhw are not supported by SSE.
+  if (Subtarget.hasSSE41() || !Subtarget.hasSSE2())
     return SDValue();
 
   ShrinkMode Mode;


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