[PATCH] D24261: AMDGPU: Make some scalar instructions commutable

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added subscribers: llvm-commits, AMDGPU.
Herald added subscribers: nhaehnle, wdng, arsenm.

https://reviews.llvm.org/D24261

Files:
  lib/Target/AMDGPU/SOPInstructions.td

Index: lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- lib/Target/AMDGPU/SOPInstructions.td
+++ lib/Target/AMDGPU/SOPInstructions.td
@@ -295,6 +295,8 @@
   [(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
 } // End Uses = [SCC]
 
+
+let isCommutable = 1 in {
 def S_MIN_I32 : SOP2_32 <"s_min_i32",
   [(set i32:$sdst, (smin i32:$src0, i32:$src1))]
 >;
@@ -307,6 +309,7 @@
 def S_MAX_U32 : SOP2_32 <"s_max_u32",
   [(set i32:$sdst, (umax i32:$src0, i32:$src1))]
 >;
+} // End isCommutable = 1
 } // End Defs = [SCC]
 
 
@@ -316,6 +319,7 @@
 } // End Uses = [SCC]
 
 let Defs = [SCC] in {
+let isCommutable = 1 in {
 def S_AND_B32 : SOP2_32 <"s_and_b32",
   [(set i32:$sdst, (and i32:$src0, i32:$src1))]
 >;
@@ -339,6 +343,8 @@
 def S_XOR_B64 : SOP2_64 <"s_xor_b64",
   [(set i64:$sdst, (xor i64:$src0, i64:$src1))]
 >;
+} // End isCommutable = 1
+
 def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32">;
 def S_ANDN2_B64 : SOP2_64 <"s_andn2_b64">;
 def S_ORN2_B32 : SOP2_32 <"s_orn2_b32">;
@@ -379,8 +385,9 @@
   [(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
 def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
 def S_MUL_I32 : SOP2_32 <"s_mul_i32",
-  [(set i32:$sdst, (mul i32:$src0, i32:$src1))]
->;
+  [(set i32:$sdst, (mul i32:$src0, i32:$src1))]> {
+  let isCommutable = 1;
+}
 
 } // End AddedComplexity = 1
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D24261.70415.patch
Type: text/x-patch
Size: 1387 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160906/cba7de1e/attachment.bin>