[PATCH] D24216: AMDGPU: Partially fix control flow at -O0
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 3 12:33:13 PDT 2016
arsenm created this revision.
arsenm added subscribers: llvm-commits, AMDGPU.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nhaehnle, wdng, arsenm, qcolombet, MatzeB.
Fixes to allow spilling all registers at the end of the block
work with exec modifications. Don't emit s_and_saveexec_b64 for
if lowering, and instead emit copies. Mark control flow mask
instructions as terminators to get correct spill code placement
with fast regalloc, and then have a separate optimization pass
form the saveexec.
This should work if SGPRs are spilled to VGPRs, but
will likely fail in the case that an SGPR spills to memory
and no workitem takes a divergent branch.
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