[PATCH] D24146: AMDGPU: Fix spilling of m0

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: nhaehnle, wdng, arsenm, qcolombet.

readlane/writelane do not support using m0 as the output/input.
Constrain the register class of spill vregs to try to avoid this,
but also handle spilling of the physreg when necessary by inserting
an additional copy to a normal SGPR.

https://reviews.llvm.org/D24146

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/m0-spill.ll
  test/CodeGen/AMDGPU/spill-m0.ll

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