[PATCH] D23897: [SelectionDAG] Generate vector_shuffle nodes for undersized result vector sizes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 31 06:33:07 PDT 2016
RKSimon added a comment.
Thanks for working on this - we don't do much to improve shuffles of concat/inserted subvectors at all yet.
Comment at: lib/Target/X86/X86ISelLowering.cpp:26349
@@ +26348,3 @@
+ // We only care about shuffles of 128/256-bit vectors of i32/i64.
+ if (!VT.is128BitVector() && !VT.is256BitVector())
You need an early out for !isa<ShuffleVectorSDNode>(N) as I think we can get here from target shuffle nodes as well as shufflevector nodes.
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