[PATCH] D16452: [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM. Add the relevant disassembler tests when you commit.


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Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1848
@@ -1840,3 +1847,3 @@
   }
-
-  if (MCID.mayLoad() || MCID.mayStore()) {
+  bool isPCRelativeLoad = (MCID.TSFlags & MipsII::isPCRelativeLoad) != 0;
+  if ((MCID.mayLoad() || MCID.mayStore()) && !isPCRelativeLoad) {
----------------
Add a space before this line for vertical separation, so it's clear the the following code is unrelated to the block above.

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Comment at: lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h:124-126
@@ -124,1 +123,5 @@
+    HasForbiddenSlot = 1 << 5,
+    /// isPCRelativeLoad - Load instruction without both source and
+    ///                    destination registers.
+    isPCRelativeLoad = 1 << 6
 
----------------
Nit: Style, capitalize the first letter in IsPCRelativeLoad.

A better description is 'A Load instruction with implicit source register ($pc) with explicit offset and destination register'.

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Comment at: lib/Target/Mips/MipsInstrFormats.td:101
@@ -100,1 +100,3 @@
   bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
+  bit isPCRelativeLoad = 0; // Load instruction without both source and
+                            // destination registers.
----------------
See my comment about IsPCRelativeLoad in MipsBaseInfo.h


https://reviews.llvm.org/D16452