[llvm] r280193 - [X86] Regenerate a test using update_llc_test_checks.py.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 30 22:37:47 PDT 2016
Author: ctopper
Date: Wed Aug 31 00:37:47 2016
New Revision: 280193
URL: http://llvm.org/viewvc/llvm-project?rev=280193&view=rev
Log:
[X86] Regenerate a test using update_llc_test_checks.py.
Modified:
llvm/trunk/test/CodeGen/X86/avx512vl-logic.ll
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-logic.ll?rev=280193&r1=280192&r2=280193&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-logic.ll Wed Aug 31 00:37:47 2016
@@ -1,11 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl | FileCheck %s
; 256-bit
-; CHECK-LABEL: vpandd256
-; CHECK: vpandd %ymm
-; CHECK: ret
define <8 x i32> @vpandd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandd256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -13,10 +16,12 @@ entry:
ret <8 x i32> %x
}
-; CHECK-LABEL: vpandnd256
-; CHECK: vpandnd %ymm
-; CHECK: ret
define <8 x i32> @vpandnd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandnd256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm1
+; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -25,10 +30,12 @@ entry:
ret <8 x i32> %x
}
-; CHECK-LABEL: vpord256
-; CHECK: vpord %ymm
-; CHECK: ret
define <8 x i32> @vpord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpord256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -36,10 +43,12 @@ entry:
ret <8 x i32> %x
}
-; CHECK-LABEL: vpxord256
-; CHECK: vpxord %ymm
-; CHECK: ret
define <8 x i32> @vpxord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpxord256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -47,10 +56,12 @@ entry:
ret <8 x i32> %x
}
-; CHECK-LABEL: vpandq256
-; CHECK: vpandq %ymm
-; CHECK: ret
define <4 x i64> @vpandq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandq256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpandq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
@@ -58,10 +69,12 @@ entry:
ret <4 x i64> %x
}
-; CHECK-LABEL: vpandnq256
-; CHECK: vpandnq %ymm
-; CHECK: ret
define <4 x i64> @vpandnq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandnq256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpandnq %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
@@ -70,10 +83,12 @@ entry:
ret <4 x i64> %x
}
-; CHECK-LABEL: vporq256
-; CHECK: vporq %ymm
-; CHECK: ret
define <4 x i64> @vporq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vporq256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vporq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
@@ -81,10 +96,12 @@ entry:
ret <4 x i64> %x
}
-; CHECK-LABEL: vpxorq256
-; CHECK: vpxorq %ymm
-; CHECK: ret
define <4 x i64> @vpxorq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpxorq256:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-NEXT: vpxorq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
@@ -94,10 +111,12 @@ entry:
; 128-bit
-; CHECK-LABEL: vpandd128
-; CHECK: vpandd %xmm
-; CHECK: ret
define <4 x i32> @vpandd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandd128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
@@ -105,10 +124,12 @@ entry:
ret <4 x i32> %x
}
-; CHECK-LABEL: vpandnd128
-; CHECK: vpandnd %xmm
-; CHECK: ret
define <4 x i32> @vpandnd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandnd128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpandnd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
@@ -117,10 +138,12 @@ entry:
ret <4 x i32> %x
}
-; CHECK-LABEL: vpord128
-; CHECK: vpord %xmm
-; CHECK: ret
define <4 x i32> @vpord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpord128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
@@ -128,10 +151,12 @@ entry:
ret <4 x i32> %x
}
-; CHECK-LABEL: vpxord128
-; CHECK: vpxord %xmm
-; CHECK: ret
define <4 x i32> @vpxord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpxord128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
@@ -139,10 +164,12 @@ entry:
ret <4 x i32> %x
}
-; CHECK-LABEL: vpandq128
-; CHECK: vpandq %xmm
-; CHECK: ret
define <2 x i64> @vpandq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandq128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpandq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <2 x i64> %a, <i64 1, i64 1>
@@ -150,10 +177,12 @@ entry:
ret <2 x i64> %x
}
-; CHECK-LABEL: vpandnq128
-; CHECK: vpandnq %xmm
-; CHECK: ret
define <2 x i64> @vpandnq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandnq128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpandnq %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <2 x i64> %a, <i64 1, i64 1>
@@ -162,10 +191,12 @@ entry:
ret <2 x i64> %x
}
-; CHECK-LABEL: vporq128
-; CHECK: vporq %xmm
-; CHECK: ret
define <2 x i64> @vporq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vporq128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vporq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <2 x i64> %a, <i64 1, i64 1>
@@ -173,10 +204,12 @@ entry:
ret <2 x i64> %x
}
-; CHECK-LABEL: vpxorq128
-; CHECK: vpxorq %xmm
-; CHECK: ret
define <2 x i64> @vpxorq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpxorq128:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpxorq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
entry:
; Force the execution domain with an add.
%a2 = add <2 x i64> %a, <i64 1, i64 1>
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