[llvm] r280022 - [PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomics
Hal Finkel via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 29 17:25:43 PDT 2016
Ah, missing a target triple I imagine, and you're on Darwin; will fix...
-Hal
----- Original Message -----
> From: "Duncan P. N. Exon Smith" <dexonsmith at apple.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "llvm-commits" <llvm-commits at lists.llvm.org>, "Akira Hatanaka" <ahatanaka at apple.com>
> Sent: Monday, August 29, 2016 7:22:28 PM
> Subject: Re: [llvm] r280022 - [PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomics
>
> Hi Hal,
>
>
> This is failing locally for me:
>
> FAIL: LLVM :: CodeGen/PowerPC/atomic-2.ll (6659 of 17802)
> ******************** TEST 'LLVM :: CodeGen/PowerPC/atomic-2.ll'
> FAILED ********************
>
> Command Output (stderr):
> --
> Assertion failed: (Section && "Cannot switch to a null section!"),
> function SwitchSection, file
> /Users/dexonsmith/data/llvm/staging/lib/MC/MCStreamer.cpp, line 805.
> Stack dump:
> 0. Program arguments:
> /Users/dexonsmith/data/llvm.symbols+asserts/staging/./bin/llc
> -march=ppc64le
> FileCheck error: '-' is empty.
> FileCheck command line:
> /Users/dexonsmith/data/llvm.symbols+asserts/staging/./bin/FileCheck
> /Users/dexonsmith/data/llvm/staging/test/CodeGen/PowerPC/atomic-2.ll
> -check-prefix=CHECK -check-prefix=CHECK-LE
>
>
> --
>
>
> Here's the backtrace:
>
> (lldb) bt
> * thread #1: tid = 0x907b07, 0x00007ffface5bdda
> libsystem_kernel.dylib`__pthread_kill + 10, queue =
> 'com.apple.main-thread', stop reason = signal SIGABRT
> * frame #0: 0x00007ffface5bdda libsystem_kernel.dylib`__pthread_kill
> + 10
> frame #1: 0x00007fffacf46797 libsystem_pthread.dylib`pthread_kill +
> 90
> frame #2: 0x00007fffacdc1440 libsystem_c.dylib`abort + 129
> frame #3: 0x00007fffacd888b3 libsystem_c.dylib`__assert_rtn + 320
> frame #4: 0x000000010106853f
> llc`llvm::MCStreamer::SwitchSection(this=0x0000000102e22880,
> Section=0x0000000000000000, Subsection=0x0000000000000000) + 399 at
> MCStreamer.cpp:805
> frame #5: 0x00000001006e887f llc`(anonymous
> namespace)::PPCDarwinAsmPrinter::EmitStartOfAsmFile(this=<unavailable>,
> M=<unavailable>) + 255 at PPCAsmPrinter.cpp:1324
> frame #6: 0x0000000100bdd2c6
> llc`llvm::AsmPrinter::doInitialization(this=0x0000000102e22b30,
> M=0x0000000102e0d0d0) + 646 at AsmPrinter.cpp:221
> frame #7: 0x0000000100fa4ecb
> llc`llvm::FPPassManager::doInitialization(this=<unavailable>,
> M=<unavailable>) + 75 at LegacyPassManager.cpp:1552
> frame #8: 0x0000000100fa51c0
> llc`llvm::legacy::PassManagerImpl::run(llvm::Module&) + 68 at
> LegacyPassManager.cpp:1584
> frame #9: 0x0000000100fa517c
> llc`llvm::legacy::PassManagerImpl::run(this=<unavailable>,
> M=<unavailable>) + 444 at LegacyPassManager.cpp:1702
> frame #10: 0x00000001000057c7
> llc`compileModule(argv=0x00007fff5fbff9b0, Context=<unavailable>) +
> 10663 at llc.cpp:506
> frame #11: 0x0000000100002bdb llc`main(argc=<unavailable>,
> argv=<unavailable>) + 459 at llc.cpp:273
> frame #12: 0x00007fffacd2d255 libdyld.dylib`start + 1
>
>
> It looks like it's also failing on at least one bot:
> http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/
> http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/testReport/junit/LLVM/CodeGen_PowerPC/atomic_2_ll/
>
>
>
> On 2016-Aug-29, at 15:25, Hal Finkel via llvm-commits <
> llvm-commits at lists.llvm.org > wrote:
>
> Author: hfinkel
> Date: Mon Aug 29 17:25:36 2016
> New Revision: 280022
>
> URL: http://llvm.org/viewvc/llvm-project?rev=280022&view=rev
> Log:
> [PowerPC] Fix i8/i16 atomics for little-Endian targets without
> partword atomics
>
> For little-Endian PowerPC, we generally target only P8 and later by
> default.
> However, generic (older) 64-bit configurations are still an option,
> and in that
> case, partword atomics are not available (e.g. stbcx.). To lower
> i8/i16 atomics
> without true i8/i16 atomic operations, we emulate using i32 atomics
> in
> combination with a bunch of shifting and masking, etc. The amount by
> which to
> shift in little-Endian mode is different from the amount in
> big-Endian mode (it
> is inverted -- meaning we can leave off the xor when computing the
> amount).
>
> Fixes PR22923.
>
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=280022&r1=280021&r2=280022&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 29
> 17:25:36 2016
> @@ -8513,6 +8513,7 @@ PPCTargetLowering::EmitPartwordAtomicBin
> // registers without caring whether they're 32 or 64, but here we're
> // doing actual arithmetic on the addresses.
> bool is64bit = Subtarget.isPPC64();
> + bool isLittleEndian = Subtarget.isLittleEndian();
> unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
>
> const BasicBlock *LLVM_BB = BB->getBasicBlock();
> @@ -8542,7 +8543,8 @@ PPCTargetLowering::EmitPartwordAtomicBin
> : &PPC::GPRCRegClass;
> unsigned PtrReg = RegInfo.createVirtualRegister(RC);
> unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
> - unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
> + unsigned ShiftReg =
> + isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
> unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
> unsigned MaskReg = RegInfo.createVirtualRegister(RC);
> unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
> @@ -8587,8 +8589,9 @@ PPCTargetLowering::EmitPartwordAtomicBin
> }
> BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
> .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
> - BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI),
> ShiftReg)
> - .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
> + if (!isLittleEndian)
> + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI),
> ShiftReg)
> + .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
> if (is64bit)
> BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
> .addReg(Ptr1Reg).addImm(0).addImm(61);
> @@ -9293,6 +9296,7 @@ PPCTargetLowering::EmitInstrWithCustomIn
> // since we're actually doing arithmetic on them. Other registers
> // can be 32-bit.
> bool is64bit = Subtarget.isPPC64();
> + bool isLittleEndian = Subtarget.isLittleEndian();
> bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
>
> unsigned dest = MI.getOperand(0).getReg();
> @@ -9319,7 +9323,8 @@ PPCTargetLowering::EmitInstrWithCustomIn
> : &PPC::GPRCRegClass;
> unsigned PtrReg = RegInfo.createVirtualRegister(RC);
> unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
> - unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
> + unsigned ShiftReg =
> + isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
> unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
> unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
> unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
> @@ -9374,8 +9379,9 @@ PPCTargetLowering::EmitInstrWithCustomIn
> }
> BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
> .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
> - BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI),
> ShiftReg)
> - .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
> + if (!isLittleEndian)
> + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI),
> ShiftReg)
> + .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
> if (is64bit)
> BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
> .addReg(Ptr1Reg).addImm(0).addImm(61);
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=280022&r1=280021&r2=280022&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Mon Aug 29 17:25:36
> 2016
> @@ -1,4 +1,5 @@
> -; RUN: llc < %s -march=ppc64 | FileCheck %s
> +; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=CHECK
> -check-prefix=CHECK-BE
> +; RUN: llc < %s -march=ppc64le | FileCheck %s -check-prefix=CHECK
> -check-prefix=CHECK-LE
> ; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
> ; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s
> -check-prefix=CHECK-P8U
>
> @@ -12,6 +13,8 @@ define i64 @exchange_and_add(i64* %mem,
>
> define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {
> ; CHECK-LABEL: exchange_and_add8:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lbarx
> %tmp = atomicrmw add i8* %mem, i8 %val monotonic
> ; CHECK-P8U: stbcx.
> @@ -20,6 +23,8 @@ define i8 @exchange_and_add8(i8* %mem, i
>
> define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {
> ; CHECK-LABEL: exchange_and_add16:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lharx
> %tmp = atomicrmw add i16* %mem, i16 %val monotonic
> ; CHECK-P8U: sthcx.
> @@ -38,6 +43,8 @@ define i64 @exchange_and_cmp(i64* %mem)
>
> define i8 @exchange_and_cmp8(i8* %mem) nounwind {
> ; CHECK-LABEL: exchange_and_cmp8:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lbarx
> %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
> %tmp = extractvalue { i8, i1 } %tmppair, 0
> @@ -48,6 +55,8 @@ define i8 @exchange_and_cmp8(i8* %mem) n
>
> define i16 @exchange_and_cmp16(i16* %mem) nounwind {
> ; CHECK-LABEL: exchange_and_cmp16:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lharx
> %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
> %tmp = extractvalue { i16, i1 } %tmppair, 0
> @@ -66,6 +75,8 @@ define i64 @exchange(i64* %mem, i64 %val
>
> define i8 @exchange8(i8* %mem, i8 %val) nounwind {
> ; CHECK-LABEL: exchange8:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lbarx
> %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic
> ; CHECK-P8U: stbcx.
> @@ -74,6 +85,8 @@ define i8 @exchange8(i8* %mem, i8 %val)
>
> define i16 @exchange16(i16* %mem, i16 %val) nounwind {
> ; CHECK-LABEL: exchange16:
> +; CHECK-BE: xori
> +; CHECK-LE-NOT: xori
> ; CHECK-P8U: lharx
> %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic
> ; CHECK-P8U: sthcx.
>
>
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>
--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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