[llvm] r279804 - Replace subregister uses when processing tied operands
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 29 10:54:01 PDT 2016
Hi Matt,
This is still failing. Could you take a look?
-Krzysztof
On 8/26/2016 10:45 AM, Krzysztof Parzyszek wrote:
> This actually fails on Hexagon:
>
> --- two-crash.ll ---
> target triple = "hexagon"
>
> define i64 @fred(i64 %x) local_unnamed_addr #0 {
> entry:
> %t.sroa.0.0.extract.trunc = trunc i64 %x to i32
> %t4.sroa.4.0.extract.shift = lshr i64 %x, 16
> %add11 = add i32 0, %t.sroa.0.0.extract.trunc
> %t14.sroa.3.0.extract.trunc = trunc i64 %t4.sroa.4.0.extract.shift to i32
> %t14.sroa.4.0.extract.shift = lshr i64 %x, 24
> %add21 = add i32 %add11, %t14.sroa.3.0.extract.trunc
> %t24.sroa.3.0.extract.trunc = trunc i64 %t14.sroa.4.0.extract.shift to
> i32
> %add31 = add i32 %add21, %t24.sroa.3.0.extract.trunc
> %conv32.mask = and i32 %add31, 255
> %conv33 = zext i32 %conv32.mask to i64
> ret i64 %conv33
> }
>
> attributes #0 = { norecurse nounwind readnone }
> --------------------
>
> $ llc -march=hexagon < two-crash.ll
>
> llc: lib/CodeGen/VirtRegMap.cpp:341: bool (anonymous
> namespace)::VirtRegRewriter::readsUndefSubreg(const llvm::MachineOperand
> &) const: Assertion `SubRegIdx != 0 && LI.hasSubRanges()' failed.
>
>
> Before (ok):
> %vreg2<def,tied1> = S2_lsr_i_r_acc %vreg0:subreg_loreg<tied0>,
> %vreg0:subreg_loreg, 16; IntRegs:%vreg2 DoubleRegs:%vreg0
>
> After (bad: vreg2 has no subregisters):
> %vreg2<def> = COPY %vreg0:subreg_loreg; IntRegs:%vreg2 DoubleRegs:%vreg0
> %vreg2<def,tied1> = S2_lsr_i_r_acc %vreg2<tied0>,
> %vreg2:subreg_loreg, 16; IntRegs:%vreg2
>
> -Krzysztof
> On 8/26/2016 1:31 AM, Matt Arsenault via llvm-commits wrote:
>> Author: arsenm
>> Date: Fri Aug 26 01:31:32 2016
>> New Revision: 279804
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=279804&view=rev
>> Log:
>> Replace subregister uses when processing tied operands
>>
>> This was for some reason skipping operands that are subregisters
>> instead of keeping the same subregister index.
>>
>> v_movreld_b32 expects src0 to be the subregister of the tied
>> super register use/def.
>>
>> e.g.
>>
>> v_movreld_b32 v0, v9, <imp-def, tied3> v[0:3], <imp-use, tied2> v[0:3]
>>
>> was being replaced with
>>
>> v[4:7] = copy v[0:3]
>> v_movreld_b32 v0, v9, <imp-def, tied3> v[4:7], <imp-use, tied2> v[4:7],
>>
>> which really writes to v[0:3]
>>
>> Added:
>> llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll
>> Modified:
>> llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
>> llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll
>>
>> Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=279804&r1=279803&r2=279804&view=diff
>>
>> ==============================================================================
>>
>> --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Aug 26
>> 01:31:32 2016
>> @@ -1567,14 +1567,14 @@ TwoAddressInstructionPass::processTiedPa
>> if (!IsEarlyClobber) {
>> // Replace other (un-tied) uses of regB with LastCopiedReg.
>> for (MachineOperand &MO : MI->operands()) {
>> - if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() ==
>> SubRegB &&
>> + if (MO.isReg() && MO.getReg() == RegB &&
>> MO.isUse()) {
>> if (MO.isKill()) {
>> MO.setIsKill(false);
>> RemovedKillFlag = true;
>> }
>> MO.setReg(LastCopiedReg);
>> - MO.setSubReg(0);
>> + MO.setSubReg(MO.getSubReg());
>> }
>> }
>> }
>>
>> Added: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll?rev=279804&view=auto
>>
>> ==============================================================================
>>
>> --- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll
>> (added)
>> +++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll Fri
>> Aug 26 01:31:32 2016
>> @@ -0,0 +1,19 @@
>> +; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
>> +
>> +; FIXME: Merge into indirect-addressing-si.ll
>> +
>> +; Make sure that TwoAddressInstructions keeps src0 as subregister sub0
>> +; of the tied implicit use and def of the super register.
>> +
>> +; CHECK-LABEL: {{^}}insert_wo_offset:
>> +; CHECK: s_load_dword [[IN:s[0-9]+]]
>> +; CHECK: s_mov_b32 m0, [[IN]]
>> +; CHECK: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
>> +; CHECK-NEXT: buffer_store_dwordx4 v{{\[}}[[ELT0]]:
>> +define void @insert_wo_offset(<4 x float> addrspace(1)* %out, i32 %in) {
>> +entry:
>> + %ins = insertelement <4 x float> <float 1.0, float 2.0, float 3.0,
>> float 4.0>, float 5.0, i32 %in
>> + store <4 x float> %ins, <4 x float> addrspace(1)* %out
>> + ret void
>> +}
>> +
>>
>> Modified: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll?rev=279804&r1=279803&r2=279804&view=diff
>>
>> ==============================================================================
>>
>> --- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll (original)
>> +++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll Fri Aug
>> 26 01:31:32 2016
>> @@ -125,27 +125,32 @@ entry:
>> }
>>
>> ; CHECK-LABEL: {{^}}insert_w_offset:
>> -; CHECK: s_load_dword [[IN:s[0-9]+]]
>> -; CHECK: s_mov_b32 m0, [[IN]]
>> -; CHECK: v_movreld_b32_e32
>> -define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
>> +; CHECK-DAG: s_load_dword [[IN:s[0-9]+]]
>> +; CHECK-DAG: s_mov_b32 m0, [[IN]]
>> +; CHECK-DAG: v_mov_b32_e32 v[[ELT0:[0-9]+]], 1.0
>> +; CHECK-DAG: v_mov_b32_e32 v[[ELT1:[0-9]+]], 2.0
>> +; CHECK-DAG: v_mov_b32_e32 v[[ELT2:[0-9]+]], 0x40400000
>> +; CHECK-DAG: v_mov_b32_e32 v[[ELT3:[0-9]+]], 4.0
>> +; CHECK-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x40a00000
>> +; CHECK: v_movreld_b32_e32 v[[ELT1]], v[[INS]]
>> +; CHECK: buffer_store_dwordx4 v{{\[}}[[ELT0]]:[[ELT3]]{{\]}}
>> +define void @insert_w_offset(<4 x float> addrspace(1)* %out, i32 %in) {
>> entry:
>> %0 = add i32 %in, 1
>> %1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0,
>> float 4.0>, float 5.0, i32 %0
>> - %2 = extractelement <4 x float> %1, i32 2
>> - store float %2, float addrspace(1)* %out
>> + store <4 x float> %1, <4 x float> addrspace(1)* %out
>> ret void
>> }
>>
>> ; CHECK-LABEL: {{^}}insert_wo_offset:
>> ; CHECK: s_load_dword [[IN:s[0-9]+]]
>> ; CHECK: s_mov_b32 m0, [[IN]]
>> -; CHECK: v_movreld_b32_e32
>> -define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
>> +; CHECK: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
>> +; CHECK: buffer_store_dwordx4 v{{\[}}[[ELT0]]:
>> +define void @insert_wo_offset(<4 x float> addrspace(1)* %out, i32 %in) {
>> entry:
>> %0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0,
>> float 4.0>, float 5.0, i32 %in
>> - %1 = extractelement <4 x float> %0, i32 2
>> - store float %1, float addrspace(1)* %out
>> + store <4 x float> %0, <4 x float> addrspace(1)* %out
>> ret void
>> }
>>
>>
>>
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>
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