[PATCH] D23688: AMDGPU/SI: Implement a custom MachineSchedStrategy

[Tom Stellard via llvm-commits]

tstellarAMD updated this revision to Diff 69420.
tstellarAMD added a comment.

Remove the special case for non-compute shaders.  This will be fixed in mesa.


https://reviews.llvm.org/D23688

Files:
  lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/GCNSchedStrategy.cpp
  lib/Target/AMDGPU/GCNSchedStrategy.h
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SISchedule.td
  test/CodeGen/AMDGPU/and.ll
  test/CodeGen/AMDGPU/ctpop64.ll
  test/CodeGen/AMDGPU/ds_read2_offset_order.ll
  test/CodeGen/AMDGPU/fceil64.ll
  test/CodeGen/AMDGPU/fma-combine.ll
  test/CodeGen/AMDGPU/fmax3.f64.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/insert_vector_elt.ll
  test/CodeGen/AMDGPU/load-constant-i16.ll
  test/CodeGen/AMDGPU/load-global-i32.ll
  test/CodeGen/AMDGPU/missing-store.ll
  test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
  test/CodeGen/AMDGPU/rcp-pattern.ll
  test/CodeGen/AMDGPU/ret.ll
  test/CodeGen/AMDGPU/salu-to-valu.ll
  test/CodeGen/AMDGPU/select-vectors.ll
  test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
  test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  test/CodeGen/AMDGPU/trunc.ll
  test/CodeGen/AMDGPU/udivrem.ll
  test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

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