[PATCH] D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc

[David Chisnall via llvm-commits]

theraven added inline comments.

================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:71
@@ +70,3 @@
+  unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
+  support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
+  ++MCNumEmitted; // Keep track of the # of mi's emitted.
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The cast here is odd.  It would be cleaner to make `Bits` a `uint32_t` and then let the compiler pick the matching instantiation of `write<>`.

It might be worth a comment saying that this will need changing for variable-length instructions, too (the RISC-V spec currently allows instructions to be up to 320 bits, though I don't know of anyone who is using ones that are longer than 64 bits yet).  


https://reviews.llvm.org/D23562