[PATCH] D23560: [RISCV 3/10] Add stub backend

[David Chisnall via llvm-commits]

theraven added a comment.

A couple of small nits inline.


================
Comment at: CMakeLists.txt:276
@@ -275,2 +275,3 @@
   PowerPC
+  RISCV
   Sparc
----------------
Not really an objection, but MIPS and SPARC are both capitalised as if they were words.  It would be more consistent to call the back end RiscV, though this would be ugly.

================
Comment at: docs/CompilerWriterInfo.rst:86
@@ +85,3 @@
+------
+* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_
+
----------------
Please also add a link to the ABI spec here.

================
Comment at: lib/Target/RISCV/RISCVTargetMachine.cpp:34
@@ +33,3 @@
+  else
+    return "e-m:e-i64:64-n32-S128";
+}
----------------
Please assert `TT.isArch32Bit()` here, so that we catch fire if someone tries to use this back end for the 128-bit RISC-V variant in the future.


https://reviews.llvm.org/D23560