[PATCH] D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions

[Andrey Turetskiy via llvm-commits]

aturetsk created this revision.
aturetsk added reviewers: nadav, echristo, bruno.
aturetsk added subscribers: llvm-commits, anadolskiy.
Herald added a subscriber: mehdi_amini.

According to spec cvtdq2pd and cvtps2pd instructions don't require memory operand to be aligned to 16 bytes. This patch removes this requirement from the memory folding table.

https://reviews.llvm.org/D23919

Files:
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/peephole-cvt-sse.ll

Index: test/CodeGen/X86/peephole-cvt-sse.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/peephole-cvt-sse.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
+
+; Check that unaligned loads merge with cvtdq2pd and cvtps2pd.
+
+define <2 x double> @peephole_cvtps2pd(<4 x float>* %a0) {
+  %1 = load <4 x float>, <4 x float>* %a0, align 1
+  %2 = shufflevector <4 x float> %1, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  %3 = fpext <2 x float> %2 to <2 x double>
+  ret <2 x double> %3
+  ; CHECK-LABEL: peephole_cvtps2pd
+  ; CHECK:       cvtps2pd (%rdi), %xmm0
+}
+
+define <2 x double> @peephole_cvtdq2pd(<4 x i32>* %a0) {
+  %1 = load <4 x i32>, <4 x i32>* %a0, align 1
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %3 = sitofp <2 x i32> %2 to <2 x double>
+  ret <2 x double> %3
+  ; CHECK-LABEL: peephole_cvtdq2pd
+  ; CHECK:       cvtdq2pd (%rdi), %xmm0
+}
Index: lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- lib/Target/X86/X86InstrInfo.cpp
+++ lib/Target/X86/X86InstrInfo.cpp
@@ -477,12 +477,12 @@
     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
-    { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
+    { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          0 },
     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
-    { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
+    { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          0 },
     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },


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