[PATCH] D23614: [PPC] Generate positive FP zero using xor insn instead of loading from constant area

[Ehsan Amiri via llvm-commits]

amehsan added inline comments.

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12117
@@ +12116,3 @@
+
+bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+  return Imm.isPosZero() && Subtarget.hasVSX();
----------------
amehsan wrote:
> echristo wrote:
> > Here's a good point for a comment on things that you expect to work :)
> VT!
I don't really know what we do with f16, f80, etc. (need to check a test case). But I think it does not hurt to guard against them.


https://reviews.llvm.org/D23614