[PATCH] D23862: AMDGPU/SI: Improve register allocation hints for sopk instructions

[Tom Stellard via llvm-commits]

tstellarAMD created this revision.
tstellarAMD added a reviewer: arsenm.
tstellarAMD added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm.

For shrinking SOPK instructions, we were creating a hint to tell the
register allocator to use the register allocated for src0 for the dst
operand as well.  However, this seems to not work sometimes depending
on the order virtual registers are assigned physical registers.

To fix this, I've added a second allocation hint which does the reverse,
asks that the register allocated for dst is used for src0.

https://reviews.llvm.org/D23862

Files:
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  test/CodeGen/AMDGPU/shl_add_constant.ll

Index: test/CodeGen/AMDGPU/shl_add_constant.ll
===================================================================
--- test/CodeGen/AMDGPU/shl_add_constant.ll
+++ test/CodeGen/AMDGPU/shl_add_constant.ll
@@ -74,8 +74,8 @@
 ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]]
-; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
+; SI: s_addk_i32 [[TMP]], 0x3d8
+; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
 ; SI: buffer_store_dword [[VRESULT]]
 
 define void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
Index: lib/Target/AMDGPU/SIShrinkInstructions.cpp
===================================================================
--- lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -282,6 +282,7 @@
         if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) &&
             Src0.isReg()) {
           MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
+          MRI.setRegAllocationHint(Src0.getReg(), 0, Dest.getReg());
           continue;
         }
 


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