[llvm] r279600 - MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 23 18:32:42 PDT 2016
Author: matze
Date: Tue Aug 23 20:32:41 2016
New Revision: 279600
URL: http://llvm.org/viewvc/llvm-project?rev=279600&view=rev
Log:
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.
Differential Revision: http://reviews.llvm.org/D22722
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir
llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir
llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir
llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir
llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir
llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir
llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir
llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir
llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir
llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue Aug 23 20:32:41 2016
@@ -389,7 +389,6 @@ struct MachineFunction {
bool RegBankSelected = false;
bool Selected = false;
// Register information
- bool IsSSA = false;
bool TracksRegLiveness = false;
bool TracksSubRegLiveness = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters;
@@ -415,7 +414,6 @@ template <> struct MappingTraits<Machine
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
- YamlIO.mapOptional("isSSA", MF.IsSSA);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters);
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 23 20:32:41 2016
@@ -289,9 +289,25 @@ static bool hasPHI(const MachineFunction
return false;
}
+static bool isSSA(const MachineFunction &MF) {
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
+ if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg))
+ return false;
+ }
+ return true;
+}
+
void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
+ MachineFunctionProperties &Properties = MF.getProperties();
if (!hasPHI(MF))
- MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+ Properties.set(MachineFunctionProperties::Property::NoPHIs);
+
+ if (isSSA(MF))
+ Properties.set(MachineFunctionProperties::Property::IsSSA);
+ else
+ Properties.clear(MachineFunctionProperties::Property::IsSSA);
}
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
@@ -382,9 +398,6 @@ bool MIRParserImpl::initializeRegisterIn
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- assert(RegInfo.isSSA());
- if (!YamlMF.IsSSA)
- RegInfo.leaveSSA();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
RegInfo.invalidateLiveness();
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Aug 23 20:32:41 2016
@@ -212,7 +212,6 @@ void MIRPrinter::print(const MachineFunc
void MIRPrinter::convert(yaml::MachineFunction &MF,
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
- MF.IsSSA = RegInfo.isSSA();
MF.TracksRegLiveness = RegInfo.tracksLiveness();
MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug 23 20:32:41 2016
@@ -580,7 +580,8 @@ void
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
FirstTerminator = nullptr;
- if (MRI->isSSA()) {
+ if (!MF->getProperties().hasProperty(
+ MachineFunctionProperties::Property::NoPHIs)) {
// If this block has allocatable physical registers live-in, check that
// it is an entry block or landing pad.
for (const auto &LI : MBB->liveins()) {
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Tue Aug 23 20:32:41 2016
@@ -74,7 +74,6 @@
# Also check that we constrain the register class of the COPY to GPR32.
# CHECK-LABEL: name: add_s32_gpr
name: add_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -104,7 +103,6 @@ body: |
# Same as add_s32_gpr, for 64-bit operations.
# CHECK-LABEL: name: add_s64_gpr
name: add_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -134,7 +132,6 @@ body: |
# Same as add_s32_gpr, for G_SUB operations.
# CHECK-LABEL: name: sub_s32_gpr
name: sub_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -164,7 +161,6 @@ body: |
# Same as add_s64_gpr, for G_SUB operations.
# CHECK-LABEL: name: sub_s64_gpr
name: sub_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -194,7 +190,6 @@ body: |
# Same as add_s32_gpr, for G_OR operations.
# CHECK-LABEL: name: or_s32_gpr
name: or_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -224,7 +219,6 @@ body: |
# Same as add_s64_gpr, for G_OR operations.
# CHECK-LABEL: name: or_s64_gpr
name: or_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -254,7 +248,6 @@ body: |
# Same as add_s32_gpr, for G_XOR operations.
# CHECK-LABEL: name: xor_s32_gpr
name: xor_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -284,7 +277,6 @@ body: |
# Same as add_s64_gpr, for G_XOR operations.
# CHECK-LABEL: name: xor_s64_gpr
name: xor_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -314,7 +306,6 @@ body: |
# Same as add_s32_gpr, for G_AND operations.
# CHECK-LABEL: name: and_s32_gpr
name: and_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -344,7 +335,6 @@ body: |
# Same as add_s64_gpr, for G_AND operations.
# CHECK-LABEL: name: and_s64_gpr
name: and_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -374,7 +364,6 @@ body: |
# Same as add_s32_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s32_gpr
name: shl_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -404,7 +393,6 @@ body: |
# Same as add_s64_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s64_gpr
name: shl_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -434,7 +422,6 @@ body: |
# Same as add_s32_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s32_gpr
name: lshr_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -464,7 +451,6 @@ body: |
# Same as add_s64_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s64_gpr
name: lshr_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -494,7 +480,6 @@ body: |
# Same as add_s32_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s32_gpr
name: ashr_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -524,7 +509,6 @@ body: |
# Same as add_s64_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s64_gpr
name: ashr_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -554,7 +538,6 @@ body: |
# there is only MADDWrrr, and we have to use the WZR physreg.
# CHECK-LABEL: name: mul_s32_gpr
name: mul_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -584,7 +567,6 @@ body: |
# Same as mul_s32_gpr for the s64 type.
# CHECK-LABEL: name: mul_s64_gpr
name: mul_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -614,7 +596,6 @@ body: |
# Same as add_s32_gpr, for G_SDIV operations.
# CHECK-LABEL: name: sdiv_s32_gpr
name: sdiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -644,7 +625,6 @@ body: |
# Same as add_s64_gpr, for G_SDIV operations.
# CHECK-LABEL: name: sdiv_s64_gpr
name: sdiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -674,7 +654,6 @@ body: |
# Same as add_s32_gpr, for G_UDIV operations.
# CHECK-LABEL: name: udiv_s32_gpr
name: udiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -704,7 +683,6 @@ body: |
# Same as add_s64_gpr, for G_UDIV operations.
# CHECK-LABEL: name: udiv_s64_gpr
name: udiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -734,7 +712,6 @@ body: |
# Check that we select a s32 FPR G_FADD into FADDSrr.
# CHECK-LABEL: name: fadd_s32_gpr
name: fadd_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -763,7 +740,6 @@ body: |
---
# CHECK-LABEL: name: fadd_s64_gpr
name: fadd_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -792,7 +768,6 @@ body: |
---
# CHECK-LABEL: name: fsub_s32_gpr
name: fsub_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -821,7 +796,6 @@ body: |
---
# CHECK-LABEL: name: fsub_s64_gpr
name: fsub_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -850,7 +824,6 @@ body: |
---
# CHECK-LABEL: name: fmul_s32_gpr
name: fmul_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -879,7 +852,6 @@ body: |
---
# CHECK-LABEL: name: fmul_s64_gpr
name: fmul_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -908,7 +880,6 @@ body: |
---
# CHECK-LABEL: name: fdiv_s32_gpr
name: fdiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -937,7 +908,6 @@ body: |
---
# CHECK-LABEL: name: fdiv_s64_gpr
name: fdiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -966,7 +936,6 @@ body: |
---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br
-isSSA: true
legalized: true
regBankSelected: true
@@ -984,7 +953,6 @@ body: |
---
# CHECK-LABEL: name: load_s64_gpr
name: load_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -1010,7 +978,6 @@ body: |
---
# CHECK-LABEL: name: load_s32_gpr
name: load_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -1036,7 +1003,6 @@ body: |
---
# CHECK-LABEL: name: store_s64_gpr
name: store_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -1064,7 +1030,6 @@ body: |
---
# CHECK-LABEL: name: store_s32_gpr
name: store_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
@@ -1092,7 +1057,6 @@ body: |
---
# CHECK-LABEL: name: frame_index
name: frame_index
-isSSA: true
legalized: true
regBankSelected: true
@@ -1117,9 +1081,7 @@ body: |
# CHECK: legalized: true
# CHECK-NEXT: regBankSelected: true
# CHECK-NEXT: selected: true
-# CHECK-NEXT: isSSA: true
name: selected_property
-isSSA: true
legalized: true
regBankSelected: true
selected: false
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Tue Aug 23 20:32:41 2016
@@ -63,7 +63,6 @@
# Check that we assign a relevant register bank for %0.
# Based on the type i32, this should be gpr.
name: defaultMapping
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -81,7 +80,6 @@ body: |
# Based on the type <2 x i32>, this should be fpr.
# FPR is used for both floating point and vector registers.
name: defaultMappingVector
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
@@ -99,7 +97,6 @@ body: |
# Indeed based on the source of the copy it should live
# in FPR, but at the use, it should be GPR.
name: defaultMapping1Repair
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
@@ -120,7 +117,6 @@ body: |
# Check that we repair the assignment for %0 differently for both uses.
name: defaultMapping2Repairs
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
@@ -147,7 +143,6 @@ body: |
# requires that it lives in GPR. Make sure regbankselect
# fixes that.
name: defaultMappingDefRepair
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -169,7 +164,6 @@ body: |
---
# Check that we are able to propagate register banks from phis.
name: phiPropagation
-isSSA: true
legalized: true
tracksRegLiveness: true
# CHECK: registers:
@@ -207,7 +201,6 @@ body: |
---
# Make sure we can repair physical register uses as well.
name: defaultMappingUseRepairPhysReg
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -229,7 +222,6 @@ body: |
---
# Make sure we can repair physical register defs.
name: defaultMappingDefRepairPhysReg
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -250,7 +242,6 @@ body: |
# Check that the greedy mode is able to switch the
# G_OR instruction from fpr to gpr.
name: greedyMappingOr
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -297,7 +288,6 @@ body: |
# G_OR instruction from fpr to gpr, while still honoring
# %2 constraint.
name: greedyMappingOrWithConstraints
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
@@ -344,7 +334,6 @@ body: |
---
# CHECK-LABEL: name: ignoreTargetSpecificInst
name: ignoreTargetSpecificInst
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -372,9 +361,7 @@ body: |
# CHECK-LABEL: name: regBankSelected_property
# CHECK: legalized: true
# CHECK: regBankSelected: true
-# CHECK: isSSA: true
name: regBankSelected_property
-isSSA: true
legalized: true
regBankSelected: false
body: |
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir Tue Aug 23 20:32:41 2016
@@ -19,7 +19,6 @@
---
name: test_scalar_add_big
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -43,7 +42,6 @@ body: |
---
name: test_scalar_add_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -65,7 +63,6 @@ body: |
---
name: test_vector_add
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_scalar_and_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_icmp
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir Tue Aug 23 20:32:41 2016
@@ -15,7 +15,6 @@
---
name: test_constant
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -43,7 +42,6 @@ body: |
---
name: test_fconstant
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir Tue Aug 23 20:32:41 2016
@@ -9,7 +9,6 @@
---
name: test_copy
-isSSA: true
registers:
- { id: 0, class: _ }
body: |
@@ -25,7 +24,6 @@ body: |
---
name: test_targetspecific
-isSSA: true
body: |
bb.0:
; CHECK-LABEL: name: test_targetspecific
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir Tue Aug 23 20:32:41 2016
@@ -15,7 +15,6 @@
---
name: test_load
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -48,7 +47,6 @@ body: |
---
name: test_store
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_scalar_mul_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_scalar_or_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir Tue Aug 23 20:32:41 2016
@@ -10,9 +10,7 @@
# Check that we set the "legalized" property.
# CHECK-LABEL: name: legalized_property
# CHECK: legalized: true
-# CHECK: isSSA: true
name: legalized_property
-isSSA: true
legalized: false
body: |
bb.0:
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir Tue Aug 23 20:32:41 2016
@@ -13,7 +13,6 @@
---
name: test_simple
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_scalar_sub_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: test_scalar_xor_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
# CHECK: instruction: %vreg0<def>(64) = COPY
# CHECK: operand 0: %vreg0<def>
name: test
-isSSA: true
regBankSelected: true
registers:
- { id: 0, class: _ }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
---
name: test
-isSSA: true
regBankSelected: true
selected: true
registers:
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Tue Aug 23 20:32:41 2016
@@ -30,7 +30,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
@@ -88,7 +87,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Tue Aug 23 20:32:41 2016
@@ -17,7 +17,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
frameInfo:
Modified: llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir Tue Aug 23 20:32:41 2016
@@ -26,7 +26,6 @@
# CHECK: S_NOP 0, implicit %4.sub1
# CHECK: S_NOP 0, implicit undef %5.sub0
name: test0
-isSSA: true
registers:
- { id: 0, class: sreg_32 }
- { id: 1, class: sreg_32 }
@@ -84,7 +83,6 @@ body: |
# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
# CHECK: S_NOP 0, implicit undef %10
name: test1
-isSSA: true
registers:
- { id: 0, class: sreg_128 }
- { id: 1, class: sreg_128 }
@@ -163,7 +161,6 @@ body: |
# CHECK: S_NOP 0, implicit %16.sub1
name: test2
-isSSA: true
registers:
- { id: 0, class: sreg_32 }
- { id: 1, class: sreg_32 }
@@ -221,7 +218,6 @@ body: |
# CHECK: %1 = COPY %vcc
# CHECK: S_NOP 0, implicit %1
name: test3
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
@@ -242,7 +238,6 @@ body: |
# CHECK: %1 = IMPLICIT_DEF
# CHECK: S_NOP 0, implicit undef %1
name: test4
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
@@ -263,7 +258,6 @@ body: |
# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
# CHECK: S_NOP 0, implicit %1.sub1
name: test5
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
@@ -290,7 +284,6 @@ body: |
# CHECK: S_NOP 0, implicit %4.sub0
# CHECK: S_NOP 0, implicit undef %4.sub3
name: loop0
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
@@ -344,7 +337,6 @@ body: |
# CHECK: bb.2:
# CHECK: S_NOP 0, implicit %6.sub3
name: loop1
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
@@ -396,7 +388,6 @@ body: |
# CHECK: S_NOP 0, implicit %2.sub2
# CHECK: S_NOP 0, implicit %2.sub3
name: loop2
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Tue Aug 23 20:32:41 2016
@@ -81,7 +81,6 @@ alignment: 1
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
---
name: baz
-isSSA: true
registers:
- { id: 0, class: _ }
body: |
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir Tue Aug 23 20:32:41 2016
@@ -11,7 +11,6 @@
---
name: bar
-isSSA: true
registers:
- { id: 0, class: gpr }
body: |
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir Tue Aug 23 20:32:41 2016
@@ -35,7 +35,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir Tue Aug 23 20:32:41 2016
@@ -22,7 +22,6 @@
# CHECK: LDRWui %x0, 1
# CHECK: STRWui %w1, %x0, 2
name: load_imp-def
-isSSA: true
body: |
bb.0.entry:
liveins: %w1, %x0
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir Tue Aug 23 20:32:41 2016
@@ -15,7 +15,6 @@
...
---
name: stack_local
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64common }
Modified: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir Tue Aug 23 20:32:41 2016
@@ -92,7 +92,6 @@ alignment: 1
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir Tue Aug 23 20:32:41 2016
@@ -23,7 +23,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
# CHECK: frameInfo:
@@ -49,7 +48,6 @@ body: |
...
---
name: test2
-isSSA: true
tracksRegLiveness: true
# CHECK: test2
Modified: llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir Tue Aug 23 20:32:41 2016
@@ -17,8 +17,7 @@
...
---
# CHECK: name: foo
-# CHECK: isSSA: false
-# CHECK-NEXT: tracksRegLiveness: false
+# CHECK: tracksRegLiveness: false
# CHECK-NEXT: tracksSubRegLiveness: false
# CHECK: ...
name: foo
@@ -27,12 +26,10 @@ body: |
...
---
# CHECK: name: bar
-# CHECK: isSSA: false
-# CHECK-NEXT: tracksRegLiveness: true
+# CHECK: tracksRegLiveness: true
# CHECK-NEXT: tracksSubRegLiveness: true
# CHECK: ...
name: bar
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: true
body: |
Modified: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir Tue Aug 23 20:32:41 2016
@@ -177,7 +177,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -225,7 +224,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -271,7 +269,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -321,7 +318,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -371,7 +367,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -421,7 +416,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -471,7 +465,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -521,7 +514,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
@@ -635,7 +627,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
Modified: llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir Tue Aug 23 20:32:41 2016
@@ -20,7 +20,6 @@
...
---
name: main
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir Tue Aug 23 20:32:41 2016
@@ -39,7 +39,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir Tue Aug 23 20:32:41 2016
@@ -39,7 +39,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir Tue Aug 23 20:32:41 2016
@@ -13,7 +13,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir Tue Aug 23 20:32:41 2016
@@ -18,7 +18,6 @@
---
name: test_vregs
-isSSA: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
@@ -50,7 +49,6 @@ body: |
---
name: test_unsized
-isSSA: true
body: |
bb.0:
successors: %bb.0
Modified: llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir Tue Aug 23 20:32:41 2016
@@ -50,7 +50,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
@@ -72,7 +71,6 @@ body: |
...
---
name: test_typed_immediates
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir Tue Aug 23 20:32:41 2016
@@ -34,7 +34,6 @@
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
frameInfo:
maxAlignment: 16
Modified: llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir Tue Aug 23 20:32:41 2016
@@ -41,7 +41,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir Tue Aug 23 20:32:41 2016
@@ -46,7 +46,6 @@
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
frameInfo:
maxAlignment: 16
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir Tue Aug 23 20:32:41 2016
@@ -15,7 +15,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir Tue Aug 23 20:32:41 2016
@@ -17,7 +17,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir Tue Aug 23 20:32:41 2016
@@ -7,7 +7,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir Tue Aug 23 20:32:41 2016
@@ -16,7 +16,6 @@
# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir Tue Aug 23 20:32:41 2016
@@ -14,7 +14,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
# CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir Tue Aug 23 20:32:41 2016
@@ -4,7 +4,6 @@
---
name: test_size_physreg
-isSSA: true
registers:
body: |
bb.0.entry:
Modified: llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir Tue Aug 23 20:32:41 2016
@@ -4,7 +4,6 @@
---
name: test_size_regclass
-isSSA: true
registers:
- { id: 0, class: gr32 }
body: |
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir Tue Aug 23 20:32:41 2016
@@ -39,7 +39,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir Tue Aug 23 20:32:41 2016
@@ -12,7 +12,6 @@
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir Tue Aug 23 20:32:41 2016
@@ -10,7 +10,6 @@
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir Tue Aug 23 20:32:41 2016
@@ -31,7 +31,6 @@
...
---
name: bar
-isSSA: true
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
@@ -65,7 +64,6 @@ body: |
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Tue Aug 23 20:32:41 2016
@@ -46,7 +46,6 @@ alignment: 4
exposesReturnsTwice: false
hasInlineAsm: true
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Tue Aug 23 20:32:41 2016
@@ -28,7 +28,6 @@ alignment: 4
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
frameInfo:
Modified: llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir Tue Aug 23 20:32:41 2016
@@ -40,7 +40,6 @@ name: main
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir Tue Aug 23 20:32:41 2016
@@ -34,7 +34,6 @@ alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
Modified: llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir (original)
+++ llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir Tue Aug 23 20:32:41 2016
@@ -20,7 +20,6 @@
---
name: foo
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Modified: llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir (original)
+++ llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir Tue Aug 23 20:32:41 2016
@@ -39,7 +39,6 @@
---
name: test_movb_killed
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -56,7 +55,6 @@ body: |
---
name: test_movb_impuse
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -73,7 +71,6 @@ body: |
---
name: test_movb_impdef_gr64
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -90,7 +87,6 @@ body: |
---
name: test_movb_impdef_gr32
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -107,7 +103,6 @@ body: |
---
name: test_movb_impdef_gr16
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -124,7 +119,6 @@ body: |
---
name: test_movw_impdef_gr32
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -141,7 +135,6 @@ body: |
---
name: test_movw_impdef_gr64
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir Tue Aug 23 20:32:41 2016
@@ -130,7 +130,6 @@ body: |
name: imp_null_check_with_bitwise_op_1
alignment: 4
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Tue Aug 23 20:32:41 2016
@@ -159,7 +159,6 @@ alignment: 4
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279600&r1=279599&r2=279600&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Tue Aug 23 20:32:41 2016
@@ -161,7 +161,6 @@ alignment: 4
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
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