[PATCH] D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc

[Philip Reames via llvm-commits]

reames added a subscriber: reames.

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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:27
@@ +26,3 @@
+class RISCVAsmBackend : public MCAsmBackend {
+  uint8_t OSABI;
+  bool Is64Bit;
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What values can this take?  Is this an enum, or a bitmask?  

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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:50
@@ +49,3 @@
+
+  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCInst &Res) const override {}
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Should this function ever be called?  If not, llvm_unreachable.

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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp:21
@@ +20,3 @@
+RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) {
+  PointerSize = CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4;
+  CommentString = "#";
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OT for this patch, but does the use of a single variable CalleeSaveStackSlotSize imply that we assume all registers which are callee saved have a fixed spill size?  This seems strange for architectures which have multiple register classes with different sizes.  


https://reviews.llvm.org/D23562