[llvm] r279302 - [Hexagon] Allow i1 values for 'r' constraint in inline-asm

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Aug 19 14:17:28 2016
New Revision: 279302

URL: http://llvm.org/viewvc/llvm-project?rev=279302&view=rev
Log:
[Hexagon] Allow i1 values for 'r' constraint in inline-asm

Added:
    llvm/trunk/test/CodeGen/Hexagon/inline-asm-i1.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=279302&r1=279301&r2=279302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Aug 19 14:17:28 2016
@@ -2987,9 +2987,10 @@ HexagonTargetLowering::getRegForInlineAs
        switch (VT.SimpleTy) {
        default:
          llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
-       case MVT::i32:
-       case MVT::i16:
+       case MVT::i1:
        case MVT::i8:
+       case MVT::i16:
+       case MVT::i32:
        case MVT::f32:
          return std::make_pair(0U, &Hexagon::IntRegsRegClass);
        case MVT::i64:

Added: llvm/trunk/test/CodeGen/Hexagon/inline-asm-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/inline-asm-i1.ll?rev=279302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/inline-asm-i1.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/inline-asm-i1.ll Fri Aug 19 14:17:28 2016
@@ -0,0 +1,10 @@
+target triple = "hexagon"
+
+define hidden void @fred() #0 {
+entry:
+  %0 = call { i32, i32 } asm sideeffect " $0 = usr\0A $1 = $2\0A $0 = insert($1, #1, #16)\0Ausr = $0 \0A", "=&r,=&r,r"(i1 undef) #1
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }
+attributes #1 = { nounwind }