[llvm] r279272 - [Hexagon] Enforce LLSC packetization rules

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Aug 19 11:57:05 2016
New Revision: 279272

URL: http://llvm.org/viewvc/llvm-project?rev=279272&view=rev
Log:
[Hexagon] Enforce LLSC packetization rules

Ensure that load locked and store conditional instructions are only
packetized with ALU32 instructions.

Patch by Ben Craig.

Added:
    llvm/trunk/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=279272&r1=279271&r2=279272&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Fri Aug 19 11:57:05 2016
@@ -1031,6 +1031,24 @@ static bool cannotCoexistAsymm(const Mac
     return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
            MJ.isCall() || MJ.isTerminator();
 
+  switch (MI.getOpcode()) {
+  case (Hexagon::S2_storew_locked):
+  case (Hexagon::S4_stored_locked):
+  case (Hexagon::L2_loadw_locked):
+  case (Hexagon::L4_loadd_locked):
+  case (Hexagon::Y4_l2fetch): {
+    // These instructions can only be grouped with ALU32 or non-floating-point
+    // XTYPE instructions.  Since there is no convenient way of identifying fp
+    // XTYPE instructions, only allow grouping with ALU32 for now.
+    unsigned TJ = HII.getType(MJ);
+    if (TJ != HexagonII::TypeALU32)
+      return true;
+    break;
+  }
+  default:
+    break;
+  }
+
   // "False" really means that the quick check failed to determine if
   // I and J cannot coexist.
   return false;

Added: llvm/trunk/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll?rev=279272&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll Fri Aug 19 11:57:05 2016
@@ -0,0 +1,12 @@
+; RUN: llc -march=hexagon < %s
+target triple = "hexagon-unknown--elf"
+
+; Function Attrs: norecurse nounwind
+define void @_Z4lockv() #0 {
+entry:
+  %__shared_owners = alloca i32, align 4
+  %0 = cmpxchg weak i32* %__shared_owners, i32 0, i32 1 seq_cst seq_cst
+  ret void
+}
+
+attributes #0 = { nounwind }