[llvm] r279267 - [Hexagon] Fix incorrect generation of S4_subi_asl_ri
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 19 09:35:05 PDT 2016
Author: kparzysz
Date: Fri Aug 19 11:35:05 2016
New Revision: 279267
URL: http://llvm.org/viewvc/llvm-project?rev=279267&view=rev
Log:
[Hexagon] Fix incorrect generation of S4_subi_asl_ri
Patch by Jyotsna Verma.
Added:
llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=279267&r1=279266&r2=279267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Fri Aug 19 11:35:05 2016
@@ -2681,13 +2681,11 @@ def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu
// Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
hasNewValue = 1, opNewValue = 0 in
-class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
- bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
+class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr,
+ bits<2> MajOp, InstrItinClass Itin>
: MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
"$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
- [(set (i32 IntRegs:$Rd),
- (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
- "$Rd = $Rx", Itin> {
+ [], "$Rd = $Rx", Itin> {
bits<5> Rd;
bits<8> u8;
@@ -2706,21 +2704,38 @@ class T_S4_ShiftOperate<string MnOp, str
let Inst{2-1} = MajOp;
}
-multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
- InstrItinClass Itin> {
- def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
- def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
+multiclass T_ShiftOperate<string mnemonic, bits<2> MajOp, InstrItinClass Itin> {
+ def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", 0, MajOp, Itin>;
+ def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", 1, MajOp, Itin>;
}
+defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>;
+defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>;
+defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>;
+defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>;
+
+class T_Shift_CommOp_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
+ : Pat<(Op (ShOp IntRegs:$Rx, u5ImmPred:$U5), u32ImmPred:$u8),
+ (MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>;
+
let AddedComplexity = 200 in {
- defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
- defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
+ def : T_Shift_CommOp_pat <S4_addi_asl_ri, add, shl>;
+ def : T_Shift_CommOp_pat <S4_addi_lsr_ri, add, srl>;
+ def : T_Shift_CommOp_pat <S4_andi_asl_ri, and, shl>;
+ def : T_Shift_CommOp_pat <S4_andi_lsr_ri, and, srl>;
+}
+
+let AddedComplexity = 30 in {
+ def : T_Shift_CommOp_pat <S4_ori_asl_ri, or, shl>;
+ def : T_Shift_CommOp_pat <S4_ori_lsr_ri, or, srl>;
}
-let AddedComplexity = 30 in
-defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
+class T_Shift_Op_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
+ : Pat<(Op u32ImmPred:$u8, (ShOp IntRegs:$Rx, u5ImmPred:$U5)),
+ (MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>;
-defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
+def : T_Shift_Op_pat <S4_subi_asl_ri, sub, shl>;
+def : T_Shift_Op_pat <S4_subi_lsr_ri, sub, srl>;
let AddedComplexity = 200 in {
def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
Added: llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll?rev=279267&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll Fri Aug 19 11:35:05 2016
@@ -0,0 +1,70 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check if S4_subi_asl_ri is being generated correctly.
+
+; CHECK-LABEL: yes_sub_asl
+; CHECK: [[REG1:(r[0-9]+)]] = sub(#0, asl([[REG1]], #1))
+
+; CHECK-LABEL: no_sub_asl
+; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}}, #1)
+; CHECK: r{{[0-9]+}} = sub([[REG2]], r{{[0-9]+}})
+
+%struct.rtx_def = type { i16, i8 }
+
+ at this_insn_number = external global i32, align 4
+
+; Function Attrs: nounwind
+define void @yes_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
+entry:
+ %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
+ %0 = load i16, i16* %code, align 4
+ switch i16 %0, label %return [
+ i16 2, label %if.end
+ i16 5, label %if.end
+ ]
+
+if.end:
+ %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
+ %1 = load i16, i16* %code6, align 4
+ %cmp8 = icmp eq i16 %1, 56
+ %conv9 = zext i1 %cmp8 to i32
+ %2 = load i32, i32* @this_insn_number, align 4
+ %3 = mul i32 %2, -2
+ %sub = add nsw i32 %conv9, %3
+ tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
+ br label %return
+
+return:
+ ret void
+}
+
+declare void @reg_is_born(%struct.rtx_def*, i32) #1
+
+; Function Attrs: nounwind
+define void @no_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
+entry:
+ %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
+ %0 = load i16, i16* %code, align 4
+ switch i16 %0, label %return [
+ i16 2, label %if.end
+ i16 5, label %if.end
+ ]
+
+if.end:
+ %1 = load i32, i32* @this_insn_number, align 4
+ %mul = mul nsw i32 %1, 2
+ %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
+ %2 = load i16, i16* %code6, align 4
+ %cmp8 = icmp eq i16 %2, 56
+ %conv9 = zext i1 %cmp8 to i32
+ %sub = sub nsw i32 %mul, %conv9
+ tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
+ br label %return
+
+return:
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #1 = { "target-cpu"="hexagonv5" }
+attributes #2 = { nounwind }
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