[PATCH] D23677: [AArch64] Avoid materializing -1 values when generating csinv instructions.

[Eli Friedman via llvm-commits]

efriedma added inline comments.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4001
@@ +4000,3 @@
+      } else if (CFVal->isAllOnesValue() && RHSVal == CTVal &&
+                 changeIntCCToAArch64CC(CC) == AArch64CC::EQ) {
+        // If FVal is -1, we can use a CSINV to invert wzr/xzr to avoid
----------------
There are really two transformations going on here...

1. You can avoid materializing -1 using CSINV on the zero register.  (Similarly, you can avoid materializing 1 with CSINC on the zero register.)
2. You can transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.

We want to perform each of these transformations whether or not the other is possible.


https://reviews.llvm.org/D23677