[llvm] r279074 - [AArch64][GlobalISel] Select G_SDIV/G_UDIV.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 18 08:17:13 PDT 2016
Author: ab
Date: Thu Aug 18 10:17:13 2016
New Revision: 279074
URL: http://llvm.org/viewvc/llvm-project?rev=279074&view=rev
Log:
[AArch64][GlobalISel] Select G_SDIV/G_UDIV.
There is no REM instruction; that will require an expansion.
It's not obvious that should be done in select, rather than as a
(custom?) legalization.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=279074&r1=279073&r2=279074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Aug 18 10:17:13 2016
@@ -113,6 +113,10 @@ static unsigned selectBinaryOp(unsigned
return AArch64::LSRVWr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVWr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVWr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVWr;
default:
return GenericOpc;
}
@@ -134,6 +138,10 @@ static unsigned selectBinaryOp(unsigned
return AArch64::LSRVXr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVXr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVXr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVXr;
default:
return GenericOpc;
}
@@ -289,6 +297,8 @@ bool AArch64InstructionSelector::select(
case TargetOpcode::G_SHL:
case TargetOpcode::G_LSHR:
case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_SDIV:
+ case TargetOpcode::G_UDIV:
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
// Reject the various things we don't support yet.
Modified: llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp?rev=279074&r1=279073&r2=279074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp Thu Aug 18 10:17:13 2016
@@ -42,7 +42,7 @@ AArch64MachineLegalizer::AArch64MachineL
setAction(BinOp, Ty, WidenScalar);
}
- for (auto BinOp : {G_SHL, G_LSHR, G_ASHR})
+ for (auto BinOp : {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV})
for (auto Ty : {s32, s64})
setAction(BinOp, Ty, Legal);
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=279074&r1=279073&r2=279074&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Aug 18 10:17:13 2016
@@ -34,6 +34,12 @@
define void @mul_s32_gpr() { ret void }
define void @mul_s64_gpr() { ret void }
+ define void @sdiv_s32_gpr() { ret void }
+ define void @sdiv_s64_gpr() { ret void }
+
+ define void @udiv_s32_gpr() { ret void }
+ define void @udiv_s64_gpr() { ret void }
+
define void @unconditional_br() { ret void }
define void @load_s64_gpr(i64* %addr) { ret void }
@@ -593,6 +599,126 @@ body: |
...
---
+# Same as add_s32_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s32_gpr
+name: sdiv_s32_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = SDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(32) = COPY %w0
+ %1(32) = COPY %w1
+ %2(32) = G_SDIV s32 %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s64_gpr
+name: sdiv_s64_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = SDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(64) = COPY %x0
+ %1(64) = COPY %x1
+ %2(64) = G_SDIV s64 %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s32_gpr
+name: udiv_s32_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = UDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(32) = COPY %w0
+ %1(32) = COPY %w1
+ %2(32) = G_UDIV s32 %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s64_gpr
+name: udiv_s64_gpr
+isSSA: true
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = UDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(64) = COPY %x0
+ %1(64) = COPY %x1
+ %2(64) = G_UDIV s64 %0, %1
+...
+
+---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br
isSSA: true
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