[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

Minor tweak request.


================
Comment at: lib/Target/X86/X86InstrInfo.td:837
@@ -836,2 +836,3 @@
 def HasLZCNT     : Predicate<"Subtarget->hasLZCNT()">;
+def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">;
 def HasBMI       : Predicate<"Subtarget->hasBMI()">;
----------------
Move this down to the other fast/slow definitions.

================
Comment at: lib/Target/X86/X86Subtarget.cpp:257
@@ -256,2 +256,3 @@
   HasLZCNT = false;
+  HasFastLZCNT = false;
   HasBMI = false;
----------------
Move this down to the other fast/slow variables.

================
Comment at: lib/Target/X86/X86Subtarget.h:428
@@ -424,2 +427,3 @@
   bool hasLZCNT() const { return HasLZCNT; }
+  bool hasFastLZCNT() const { return HasFastLZCNT; }
   bool hasBMI() const { return HasBMI; }
----------------
Move this down to the other fast/slow functions.


https://reviews.llvm.org/D23446