[llvm] r278902 - Replace "fallthrough" comments with LLVM_FALLTHROUGH
Chandler Carruth via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 23:59:28 PDT 2016
On Tue, Aug 16, 2016 at 10:18 PM Justin Bogner via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: bogner
> Date: Wed Aug 17 00:10:15 2016
> New Revision: 278902
>
> URL: http://llvm.org/viewvc/llvm-project?rev=278902&view=rev
> Log:
> Replace "fallthrough" comments with LLVM_FALLTHROUGH
>
> This is a mechanical change of comments in switches like fallthrough,
> fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead.
>
While I fully support the intent here, the current mechanism causes *tons*
of -Wc++1z-extension warnings as a consequence of this patch...
If I can't figure out a reliable way to fix this, I'm gonna have to revert
it or something. It's made the build somewhat unusable.
>
> Modified:
> llvm/trunk/lib/Analysis/InstructionSimplify.cpp
> llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
> llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
> llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
> llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
>
> llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
> llvm/trunk/lib/IR/ConstantFold.cpp
> llvm/trunk/lib/IR/InlineAsm.cpp
> llvm/trunk/lib/IR/Value.cpp
> llvm/trunk/lib/Object/SymbolicFile.cpp
> llvm/trunk/lib/Option/OptTable.cpp
> llvm/trunk/lib/TableGen/TGLexer.cpp
> llvm/trunk/lib/TableGen/TGParser.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
> llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
> llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
> llvm/trunk/lib/Target/X86/X86FastISel.cpp
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
> llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
> llvm/trunk/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
> llvm/trunk/lib/Transforms/ObjCARC/ObjCARCContract.cpp
> llvm/trunk/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
> llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
> llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
> llvm/trunk/tools/dsymutil/DwarfLinker.cpp
> llvm/trunk/tools/llvm-readobj/ELFDumper.cpp
>
> Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
> +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Aug 17 00:10:15
> 2016
> @@ -2773,7 +2773,7 @@ static Value *SimplifyICmpInst(unsigned
> Q.CxtI, Q.DT);
> if (!KnownNonNegative)
> break;
> - // fall-through
> + LLVM_FALLTHROUGH;
> case ICmpInst::ICMP_EQ:
> case ICmpInst::ICMP_UGT:
> case ICmpInst::ICMP_UGE:
> @@ -2784,7 +2784,7 @@ static Value *SimplifyICmpInst(unsigned
> Q.CxtI, Q.DT);
> if (!KnownNonNegative)
> break;
> - // fall-through
> + LLVM_FALLTHROUGH;
> case ICmpInst::ICMP_NE:
> case ICmpInst::ICMP_ULT:
> case ICmpInst::ICMP_ULE:
> @@ -2804,7 +2804,7 @@ static Value *SimplifyICmpInst(unsigned
> Q.CxtI, Q.DT);
> if (!KnownNonNegative)
> break;
> - // fall-through
> + LLVM_FALLTHROUGH;
> case ICmpInst::ICMP_NE:
> case ICmpInst::ICMP_UGT:
> case ICmpInst::ICMP_UGE:
> @@ -2815,7 +2815,7 @@ static Value *SimplifyICmpInst(unsigned
> Q.CxtI, Q.DT);
> if (!KnownNonNegative)
> break;
> - // fall-through
> + LLVM_FALLTHROUGH;
> case ICmpInst::ICMP_EQ:
> case ICmpInst::ICMP_ULT:
> case ICmpInst::ICMP_ULE:
> @@ -2877,7 +2877,7 @@ static Value *SimplifyICmpInst(unsigned
> case Instruction::LShr:
> if (ICmpInst::isSigned(Pred))
> break;
> - // fall-through
> + LLVM_FALLTHROUGH;
> case Instruction::SDiv:
> case Instruction::AShr:
> if (!LBO->isExact() || !RBO->isExact())
>
> Modified: llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp (original)
> +++ llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp Wed Aug 17 00:10:15 2016
> @@ -537,7 +537,7 @@ bool TargetLibraryInfoImpl::isValidProto
> --NumParams;
> if (!IsSizeTTy(FTy.getParamType(NumParams)))
> return false;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case LibFunc::strcpy:
> case LibFunc::stpcpy:
> return (NumParams == 2 && FTy.getReturnType() == FTy.getParamType(0)
> &&
> @@ -549,7 +549,7 @@ bool TargetLibraryInfoImpl::isValidProto
> --NumParams;
> if (!IsSizeTTy(FTy.getParamType(NumParams)))
> return false;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case LibFunc::strncpy:
> case LibFunc::stpncpy:
> return (NumParams == 3 && FTy.getReturnType() == FTy.getParamType(0)
> &&
> @@ -642,7 +642,7 @@ bool TargetLibraryInfoImpl::isValidProto
> --NumParams;
> if (!IsSizeTTy(FTy.getParamType(NumParams)))
> return false;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case LibFunc::memcpy:
> case LibFunc::mempcpy:
> case LibFunc::memmove:
> @@ -655,7 +655,7 @@ bool TargetLibraryInfoImpl::isValidProto
> --NumParams;
> if (!IsSizeTTy(FTy.getParamType(NumParams)))
> return false;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case LibFunc::memset:
> return (NumParams == 3 && FTy.getReturnType() == FTy.getParamType(0)
> &&
> FTy.getParamType(0)->isPointerTy() &&
>
> Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
> +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Aug 17 00:10:15
> 2016
> @@ -2271,7 +2271,7 @@ std::error_code BitcodeReader::parseMeta
> }
> case bitc::METADATA_DISTINCT_NODE:
> IsDistinct = true;
> - // fallthrough...
> + LLVM_FALLTHROUGH;
> case bitc::METADATA_NODE: {
> SmallVector<Metadata *, 8> Elts;
> Elts.reserve(Record.size());
> @@ -3355,7 +3355,7 @@ std::error_code BitcodeReader::parseUseL
> break;
> case bitc::USELIST_CODE_BB:
> IsBB = true;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case bitc::USELIST_CODE_DEFAULT: {
> unsigned RecordLength = Record.size();
> if (RecordLength < 3)
>
> Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Wed Aug 17 00:10:15 2016
> @@ -1583,7 +1583,7 @@ bool MIParser::parseMachineOperand(Machi
> lex();
> break;
> }
> - // fallthrough
> + LLVM_FALLTHROUGH;
> default:
> // FIXME: Parse the MCSymbol machine operand.
> return error("expected a machine operand");
>
> Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Wed Aug 17
> 00:10:15 2016
> @@ -145,7 +145,7 @@ ScoreboardHazardRecognizer::getHazardTyp
> case InstrStage::Required:
> // Required FUs conflict with both reserved and required ones
> freeUnits &= ~ReservedScoreboard[StageCycle];
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case InstrStage::Reserved:
> // Reserved FUs can conflict only with required ones.
> freeUnits &= ~RequiredScoreboard[StageCycle];
> @@ -197,7 +197,7 @@ void ScoreboardHazardRecognizer::EmitIns
> case InstrStage::Required:
> // Required FUs conflict with both reserved and required ones
> freeUnits &= ~ReservedScoreboard[cycle + i];
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case InstrStage::Reserved:
> // Reserved FUs can conflict only with required ones.
> freeUnits &= ~RequiredScoreboard[cycle + i];
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 17
> 00:10:15 2016
> @@ -801,7 +801,7 @@ void SelectionDAGLegalize::LegalizeLoadO
> default: llvm_unreachable("This action is not supported yet!");
> case TargetLowering::Custom:
> isCustom = true;
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case TargetLowering::Legal: {
> Value = SDValue(Node, 0);
> Chain = SDValue(Node, 1);
> @@ -1598,6 +1598,7 @@ bool SelectionDAGLegalize::LegalizeSetCC
> break;
> }
> // Fallthrough if we are unsigned integer.
> + LLVM_FALLTHROUGH;
> case ISD::SETLE:
> case ISD::SETGT:
> case ISD::SETGE:
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Aug
> 17 00:10:15 2016
> @@ -1776,7 +1776,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS
> switch (BoolType) {
> case TargetLoweringBase::UndefinedBooleanContent:
> OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT),
> OVF);
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case TargetLoweringBase::ZeroOrOneBooleanContent:
> Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
> break;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 17
> 00:10:15 2016
> @@ -2481,7 +2481,7 @@ void SelectionDAG::computeKnownBits(SDVa
> default:
> if (Op.getOpcode() < ISD::BUILTIN_OP_END)
> break;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ISD::INTRINSIC_WO_CHAIN:
> case ISD::INTRINSIC_W_CHAIN:
> case ISD::INTRINSIC_VOID:
> @@ -3868,7 +3868,7 @@ SDValue SelectionDAG::getNode(unsigned O
> // Handle undef ^ undef -> 0 special case. This is a common
> // idiom (misuse).
> return getConstant(0, DL, VT);
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ISD::ADD:
> case ISD::ADDC:
> case ISD::ADDE:
>
> Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Wed Aug 17 00:10:15 2016
> @@ -483,7 +483,7 @@ void TargetPassConfig::addPassesToHandle
> // pad is shared by multiple invokes and is also a target of a normal
> // edge from elsewhere.
> addPass(createSjLjEHPreparePass());
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case ExceptionHandling::DwarfCFI:
> case ExceptionHandling::ARM:
> addPass(createDwarfEHPass(TM));
>
> Modified:
> llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> ---
> llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
> (original)
> +++
> llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
> Wed Aug 17 00:10:15 2016
> @@ -97,7 +97,8 @@ public:
> (void)p;
> assert((*p & 0x3B000000) == 0x39000000 &&
> "Only expected load / store instructions.");
> - } // fall-through
> + LLVM_FALLTHROUGH;
> + }
> case MachO::ARM64_RELOC_PAGEOFF12: {
> // Verify that the relocation points to one of the expected load /
> store
> // or add / sub instructions.
> @@ -196,7 +197,8 @@ public:
> assert((*p & 0x3B000000) == 0x39000000 &&
> "Only expected load / store instructions.");
> (void)p;
> - } // fall-through
> + LLVM_FALLTHROUGH;
> + }
> case MachO::ARM64_RELOC_PAGEOFF12: {
> // Verify that the relocation points to one of the expected load /
> store
> // or add / sub instructions.
>
> Modified: llvm/trunk/lib/IR/ConstantFold.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/ConstantFold.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/IR/ConstantFold.cpp (original)
> +++ llvm/trunk/lib/IR/ConstantFold.cpp Wed Aug 17 00:10:15 2016
> @@ -925,7 +925,7 @@ Constant *llvm::ConstantFoldBinaryInstru
> // Handle undef ^ undef -> 0 special case. This is a common
> // idiom (misuse).
> return Constant::getNullValue(C1->getType());
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case Instruction::Add:
> case Instruction::Sub:
> return UndefValue::get(C1->getType());
>
> Modified: llvm/trunk/lib/IR/InlineAsm.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/InlineAsm.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/IR/InlineAsm.cpp (original)
> +++ llvm/trunk/lib/IR/InlineAsm.cpp Wed Aug 17 00:10:15 2016
> @@ -265,7 +265,7 @@ bool InlineAsm::Verify(FunctionType *Ty,
> break;
> }
> ++NumIndirect;
> - // FALLTHROUGH for Indirect Outputs.
> + LLVM_FALLTHROUGH; // We fall through for Indirect Outputs.
> case InlineAsm::isInput:
> if (NumClobbers) return false; // inputs before
> clobbers.
> ++NumInputs;
>
> Modified: llvm/trunk/lib/IR/Value.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Value.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/IR/Value.cpp (original)
> +++ llvm/trunk/lib/IR/Value.cpp Wed Aug 17 00:10:15 2016
> @@ -449,7 +449,7 @@ static Value *stripPointerCastsAndOffset
> case PSK_InBoundsConstantIndices:
> if (!GEP->hasAllConstantIndices())
> return V;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case PSK_InBounds:
> if (!GEP->isInBounds())
> return V;
> @@ -848,7 +848,7 @@ void ValueHandleBase::ValueIsRAUWd(Value
> // virtual (or inline) interface to handle this though, so instead
> we make
> // the TrackingVH accessors guarantee that a client never sees this
> value.
>
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case Weak:
> // Weak goes to the new value, which will unlink it from Old's list.
> Entry->operator=(New);
>
> Modified: llvm/trunk/lib/Object/SymbolicFile.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/SymbolicFile.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Object/SymbolicFile.cpp (original)
> +++ llvm/trunk/lib/Object/SymbolicFile.cpp Wed Aug 17 00:10:15 2016
> @@ -36,7 +36,7 @@ Expected<std::unique_ptr<SymbolicFile>>
> case sys::fs::file_magic::bitcode:
> if (Context)
> return errorOrToExpected(IRObjectFile::create(Object, *Context));
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case sys::fs::file_magic::unknown:
> case sys::fs::file_magic::archive:
> case sys::fs::file_magic::macho_universal_binary:
>
> Modified: llvm/trunk/lib/Option/OptTable.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Option/OptTable.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Option/OptTable.cpp (original)
> +++ llvm/trunk/lib/Option/OptTable.cpp Wed Aug 17 00:10:15 2016
> @@ -317,7 +317,7 @@ static std::string getOptionHelpName(con
> case Option::SeparateClass: case Option::JoinedOrSeparateClass:
> case Option::RemainingArgsClass: case Option::RemainingArgsJoinedClass:
> Name += ' ';
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case Option::JoinedClass: case Option::CommaJoinedClass:
> case Option::JoinedAndSeparateClass:
> if (const char *MetaVarName = Opts.getOptionMetaVar(Id))
>
> Modified: llvm/trunk/lib/TableGen/TGLexer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGLexer.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/TableGen/TGLexer.cpp (original)
> +++ llvm/trunk/lib/TableGen/TGLexer.cpp Wed Aug 17 00:10:15 2016
> @@ -155,7 +155,7 @@ tgtok::TokKind TGLexer::LexToken() {
> case '0': case '1':
> if (NextChar == 'b')
> return LexNumber();
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case '2': case '3': case '4': case '5':
> case '6': case '7': case '8': case '9':
> case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
>
> Modified: llvm/trunk/lib/TableGen/TGParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/TableGen/TGParser.cpp (original)
> +++ llvm/trunk/lib/TableGen/TGParser.cpp Wed Aug 17 00:10:15 2016
> @@ -1286,6 +1286,7 @@ Init *TGParser::ParseSimpleValue(Record
> continue;
> }
> // Fallthrough to try convert this to a bit.
> + LLVM_FALLTHROUGH;
> }
> // All other values must be convertible to just a single bit.
> Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get());
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Aug 17
> 00:10:15 2016
> @@ -1179,7 +1179,8 @@ static void changeVectorFPCCToAArch64CC(
> changeFPCCToAArch64CC(CC, CondCode, CondCode2);
> break;
> case ISD::SETUO:
> - Invert = true; // Fallthrough
> + Invert = true;
> + LLVM_FALLTHROUGH;
> case ISD::SETO:
> CondCode = AArch64CC::MI;
> CondCode2 = AArch64CC::GE;
> @@ -6720,8 +6721,8 @@ static SDValue EmitVectorComparison(SDVa
> case AArch64CC::LT:
> if (!NoNans)
> return SDValue();
> - // If we ignore NaNs then we can use to the MI implementation.
> - // Fallthrough.
> + // If we ignore NaNs then we can use to the MI implementation.
> + LLVM_FALLTHROUGH;
> case AArch64CC::MI:
> if (IsZero)
> return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed Aug 17 00:10:15
> 2016
> @@ -375,7 +375,8 @@ static unsigned canFoldIntoCSel(const Ma
> // if NZCV is used, do not fold.
> if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
> return 0;
> - // fall-through to ADDXri and ADDWri.
> + // fall-through to ADDXri and ADDWri.
> + LLVM_FALLTHROUGH;
> case AArch64::ADDXri:
> case AArch64::ADDWri:
> // add x, 1 -> csinc.
> @@ -402,7 +403,8 @@ static unsigned canFoldIntoCSel(const Ma
> // if NZCV is used, do not fold.
> if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
> return 0;
> - // fall-through to SUBXrr and SUBWrr.
> + // fall-through to SUBXrr and SUBWrr.
> + LLVM_FALLTHROUGH;
> case AArch64::SUBXrr:
> case AArch64::SUBWrr: {
> // neg x -> csneg, represented as sub dst, xzr, src.
>
> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed Aug
> 17 00:10:15 2016
> @@ -3455,7 +3455,7 @@ bool AArch64AsmParser::validateInstructi
> if (RI->isSubRegisterEq(Rn, Rt2))
> return Error(Loc[1], "unpredictable LDP instruction, writeback base
> "
> "is also a destination");
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> }
> case AArch64::LDPDi:
> case AArch64::LDPQi:
>
> Modified:
> llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed
> Aug 17 00:10:15 2016
> @@ -1097,7 +1097,7 @@ static DecodeStatus DecodeExclusiveLdStI
> case AArch64::STXRB:
> case AArch64::STXRH:
> DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case AArch64::LDARW:
> case AArch64::LDARB:
> case AArch64::LDARH:
> @@ -1121,7 +1121,7 @@ static DecodeStatus DecodeExclusiveLdStI
> case AArch64::STLXRX:
> case AArch64::STXRX:
> DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case AArch64::LDARX:
> case AArch64::LDAXRX:
> case AArch64::LDXRX:
> @@ -1133,7 +1133,7 @@ static DecodeStatus DecodeExclusiveLdStI
> case AArch64::STLXPW:
> case AArch64::STXPW:
> DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case AArch64::LDAXPW:
> case AArch64::LDXPW:
> DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
> @@ -1142,7 +1142,7 @@ static DecodeStatus DecodeExclusiveLdStI
> case AArch64::STLXPX:
> case AArch64::STXPX:
> DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case AArch64::LDAXPX:
> case AArch64::LDXPX:
> DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
> @@ -1218,7 +1218,7 @@ static DecodeStatus DecodePairLdStInstru
> case AArch64::STPXpre:
> case AArch64::LDPSWpre:
> NeedsDisjointWritebackTransfer = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case AArch64::LDNPXi:
> case AArch64::STNPXi:
> case AArch64::LDPXi:
> @@ -1232,7 +1232,7 @@ static DecodeStatus DecodePairLdStInstru
> case AArch64::LDPWpre:
> case AArch64::STPWpre:
> NeedsDisjointWritebackTransfer = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case AArch64::LDNPWi:
> case AArch64::STNPWi:
> case AArch64::LDPWi:
>
> Modified: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp Wed Aug 17 00:10:15
> 2016
> @@ -586,9 +586,10 @@ void R600TargetLowering::ReplaceNodeResu
> Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));
> return;
> }
> - // Fall-through. Since we don't care about out of bounds values
> - // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
> - // considers some extra cases which are not necessary here.
> + // Since we don't care about out of bounds values we can use
> FP_TO_SINT for
> + // uints too. The DAGLegalizer code for uint considers some extra
> cases
> + // which are not necessary here.
> + LLVM_FALLTHROUGH;
> case ISD::FP_TO_SINT: {
> if (N->getValueType(0) == MVT::i1) {
> Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed Aug 17 00:10:15
> 2016
> @@ -2389,7 +2389,7 @@ SDValue SITargetLowering::LowerLOAD(SDVa
> // have the same legalization requires ments as global and private
> // loads.
> //
> - // Fall-through
> + LLVM_FALLTHROUGH;
> case AMDGPUAS::GLOBAL_ADDRESS:
> case AMDGPUAS::FLAT_ADDRESS:
> if (NumElements > 4)
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Aug 17 00:10:15 2016
> @@ -1721,7 +1721,7 @@ bool SIInstrInfo::verifyInstruction(cons
> ErrInfo = "Expected immediate, but got non-immediate";
> return false;
> }
> - // Fall-through
> + LLVM_FALLTHROUGH;
> default:
> continue;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Aug 17 00:10:15 2016
> @@ -249,7 +249,7 @@ bool ARMAsmPrinter::PrintAsmOperand(cons
> << "]";
> return false;
> }
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case 'c': // Don't print "#" before an immediate operand.
> if (!MI->getOperand(OpNum).isImm())
> return true;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Aug 17
> 00:10:15 2016
> @@ -684,7 +684,7 @@ initializeFunctionInfo(const std::vector
> case ARM::Bcc:
> isCond = true;
> UOpc = ARM::B;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::B:
> Bits = 24;
> Scale = 4;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Aug 17 00:10:15 2016
> @@ -1075,7 +1075,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, u
> TII.get(Opc), Res)
> .addReg(SrcReg).addImm(1));
> SrcReg = Res;
> - } // Fallthrough here.
> + LLVM_FALLTHROUGH;
> + }
> case MVT::i8:
> if (isThumb2) {
> if (Addr.Offset < 0 && Addr.Offset > -256 &&
> Subtarget->hasV6T2Ops())
> @@ -1848,7 +1849,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCa
> // For AAPCS ABI targets, just use VFP variant of the calling
> convention.
> return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
> }
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CallingConv::C:
> case CallingConv::CXX_FAST_TLS:
> // Use target triple & subtarget features to do actual dispatch.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed Aug 17 00:10:15 2016
> @@ -356,7 +356,7 @@ void ARMFrameLowering::emitPrologue(Mach
> GPRCS2Size += 4;
> break;
> }
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::R0:
> case ARM::R1:
> case ARM::R2:
> @@ -559,7 +559,7 @@ void ARMFrameLowering::emitPrologue(Mach
> case ARM::R12:
> if (STI.splitFramePushPop())
> break;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::R0:
> case ARM::R1:
> case ARM::R2:
> @@ -1558,7 +1558,7 @@ void ARMFrameLowering::determineCalleeSa
> switch (Reg) {
> case ARM::LR:
> LRSpilled = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::R0: case ARM::R1:
> case ARM::R2: case ARM::R3:
> case ARM::R4: case ARM::R5:
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Aug 17 00:10:15 2016
> @@ -4420,7 +4420,7 @@ SelectInlineAsmMemoryOperand(const SDVal
> case InlineAsm::Constraint_i:
> // FIXME: It seems strange that 'i' is needed here since it's
> supposed to
> // be an immediate and not a memory constraint.
> - // Fallthrough.
> + LLVM_FALLTHROUGH;
> case InlineAsm::Constraint_m:
> case InlineAsm::Constraint_o:
> case InlineAsm::Constraint_Q:
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 17 00:10:15 2016
> @@ -4906,22 +4906,22 @@ static SDValue LowerVSETCC(SDValue Op, S
> switch (SetCCOpcode) {
> default: llvm_unreachable("Illegal FP comparison");
> case ISD::SETUNE:
> - case ISD::SETNE: Invert = true; // Fallthrough
> + case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;
> case ISD::SETOEQ:
> case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
> case ISD::SETOLT:
> - case ISD::SETLT: Swap = true; // Fallthrough
> + case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETOGT:
> case ISD::SETGT: Opc = ARMISD::VCGT; break;
> case ISD::SETOLE:
> - case ISD::SETLE: Swap = true; // Fallthrough
> + case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETOGE:
> case ISD::SETGE: Opc = ARMISD::VCGE; break;
> - case ISD::SETUGE: Swap = true; // Fallthrough
> + case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
> - case ISD::SETUGT: Swap = true; // Fallthrough
> + case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
> - case ISD::SETUEQ: Invert = true; // Fallthrough
> + case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;
> case ISD::SETONE:
> // Expand this to (OLT | OGT).
> TmpOp0 = Op0;
> @@ -4930,7 +4930,9 @@ static SDValue LowerVSETCC(SDValue Op, S
> Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
> Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
> break;
> - case ISD::SETUO: Invert = true; // Fallthrough
> + case ISD::SETUO:
> + Invert = true;
> + LLVM_FALLTHROUGH;
> case ISD::SETO:
> // Expand this to (OLT | OGE).
> TmpOp0 = Op0;
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17
> 00:10:15 2016
> @@ -5425,7 +5425,7 @@ bool ARMAsmParser::parseOperand(OperandV
> return false;
> }
> // w/ a ':' after the '#', it's just like a plain ':'.
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> }
> case AsmToken::Colon: {
> S = Parser.getTok().getLoc();
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Aug 17
> 00:10:15 2016
> @@ -375,7 +375,7 @@ unsigned ARMAsmBackend::adjustFixupValue
> case ARM::fixup_arm_movt_hi16:
> if (!IsPCRel)
> Value >>= 16;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::fixup_arm_movw_lo16: {
> unsigned Hi4 = (Value & 0xF000) >> 12;
> unsigned Lo12 = Value & 0x0FFF;
> @@ -387,7 +387,7 @@ unsigned ARMAsmBackend::adjustFixupValue
> case ARM::fixup_t2_movt_hi16:
> if (!IsPCRel)
> Value >>= 16;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::fixup_t2_movw_lo16: {
> unsigned Hi4 = (Value & 0xF000) >> 12;
> unsigned i = (Value & 0x800) >> 11;
> @@ -403,7 +403,7 @@ unsigned ARMAsmBackend::adjustFixupValue
> case ARM::fixup_arm_ldst_pcrel_12:
> // ARM PC-relative values are offset by 8.
> Value -= 4;
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case ARM::fixup_t2_ldst_pcrel_12: {
> // Offset by 4, adjusted by two due to the half-word ordering of
> thumb.
> Value -= 4;
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Aug 17
> 00:10:15 2016
> @@ -1493,7 +1493,7 @@ getT2SORegOpValue(const MCInst &MI, unsi
> case ARM_AM::lsl: SBits = 0x0; break;
> case ARM_AM::lsr: SBits = 0x2; break;
> case ARM_AM::asr: SBits = 0x4; break;
> - case ARM_AM::rrx: // FALLTHROUGH
> + case ARM_AM::rrx: LLVM_FALLTHROUGH;
> case ARM_AM::ror: SBits = 0x6; break;
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Aug
> 17 00:10:15 2016
> @@ -208,7 +208,7 @@ RecordARMScatteredHalfRelocation(MachObj
> if (Asm.isThumbFunc(A))
> FixedValue &= 0xfffffffe;
> MovtBit = 1;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::fixup_t2_movw_lo16:
> ThumbBit = 1;
> break;
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Wed Aug 17 00:10:15
> 2016
> @@ -154,7 +154,7 @@ void Thumb1FrameLowering::emitPrologue(M
> GPRCS2Size += 4;
> break;
> }
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ARM::R4:
> case ARM::R5:
> case ARM::R6:
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Aug 17 00:10:15
> 2016
> @@ -651,7 +651,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineB
> case ARM::t2ADDSri: {
> if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
> return true;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> }
> case ARM::t2ADDSrr:
> return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
>
> Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp Wed Aug 17 00:10:15 2016
> @@ -172,7 +172,7 @@ void AVRRegisterInfo::eliminateFrameInde
> Opcode = AVR::ADIWRdK;
> break;
> }
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> }
> default: {
> // This opcode will get expanded into a pair of subi/sbci.
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Wed
> Aug 17 00:10:15 2016
> @@ -569,8 +569,8 @@ public:
> if (!Resolved) {
> switch ((unsigned)Fixup.getKind()) {
> case fixup_Hexagon_B22_PCREL:
> - // GetFixupCount assumes B22 won't relax
> - // Fallthrough
> + // GetFixupCount assumes B22 won't relax
> + LLVM_FALLTHROUGH;
> default:
> return false;
> break;
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp Wed Aug
> 17 00:10:15 2016
> @@ -215,7 +215,7 @@ bool HexagonShuffler::check() {
> break;
> case HexagonII::TypeJR:
> ++jumpr;
> - // Fall-through.
> + LLVM_FALLTHROUGH;
> case HexagonII::TypeJ:
> ++jumps;
> break;
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Wed Aug 17
> 00:10:15 2016
> @@ -807,7 +807,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV
> std::swap(LHS, RHS);
> break;
> case ISD::SETULE:
> - std::swap(LHS, RHS); // FALLTHROUGH
> + std::swap(LHS, RHS);
> + LLVM_FALLTHROUGH;
> case ISD::SETUGE:
> // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows
> us to
> // fold constant into instruction.
> @@ -820,7 +821,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV
> TCC = MSP430CC::COND_HS; // aka COND_C
> break;
> case ISD::SETUGT:
> - std::swap(LHS, RHS); // FALLTHROUGH
> + std::swap(LHS, RHS);
> + LLVM_FALLTHROUGH;
> case ISD::SETULT:
> // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows
> us to
> // fold constant into instruction.
> @@ -833,7 +835,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV
> TCC = MSP430CC::COND_LO; // aka COND_NC
> break;
> case ISD::SETLE:
> - std::swap(LHS, RHS); // FALLTHROUGH
> + std::swap(LHS, RHS);
> + LLVM_FALLTHROUGH;
> case ISD::SETGE:
> // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us
> to
> // fold constant into instruction.
> @@ -846,7 +849,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV
> TCC = MSP430CC::COND_GE;
> break;
> case ISD::SETGT:
> - std::swap(LHS, RHS); // FALLTHROUGH
> + std::swap(LHS, RHS);
> + LLVM_FALLTHROUGH;
> case ISD::SETLT:
> // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us
> to
> // fold constant into instruction.
>
> Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Aug
> 17 00:10:15 2016
> @@ -1662,7 +1662,7 @@ static DecodeStatus DecodeMemMMImm12(MCI
> break;
> case Mips::SC_MM:
> Inst.addOperand(MCOperand::createReg(Reg));
> - // fallthrough
> + LLVM_FALLTHROUGH;
> default:
> Inst.addOperand(MCOperand::createReg(Reg));
> if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() ==
> Mips::SWP_MM ||
>
> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed
> Aug 17 00:10:15 2016
> @@ -531,7 +531,7 @@ bool MipsELFObjectWriter::needsRelocateW
> case ELF::R_MIPS_GPREL32:
> if (cast<MCSymbolELF>(Sym).getOther() & ELF::STO_MIPS_MICROMIPS)
> return true;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ELF::R_MIPS_26:
> case ELF::R_MIPS_64:
> case ELF::R_MIPS_GPREL16:
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 00:10:15
> 2016
> @@ -2765,19 +2765,19 @@ MipsTargetLowering::LowerCall(TargetLowe
> break;
> case CCValAssign::SExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::SExt:
> Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
> break;
> case CCValAssign::ZExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::ZExt:
> Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
> break;
> case CCValAssign::AExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::AExt:
> Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
> break;
> @@ -3235,19 +3235,19 @@ MipsTargetLowering::LowerReturn(SDValue
> break;
> case CCValAssign::AExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::AExt:
> Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
> break;
> case CCValAssign::ZExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::ZExt:
> Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
> break;
> case CCValAssign::SExtUpper:
> UseUpperBits = true;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case CCValAssign::SExt:
> Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
> break;
>
> Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Wed Aug 17
> 00:10:15 2016
> @@ -1571,7 +1571,8 @@ bool PPCAsmParser::ParseOperand(OperandV
> return false;
> }
> }
> - // Fall-through to process non-register-name identifiers as expression.
> + // Fall-through to process non-register-name identifiers as
> expression.
> + LLVM_FALLTHROUGH;
> // All other expressions
> case AsmToken::LParen:
> case AsmToken::Plus:
> @@ -1644,7 +1645,7 @@ bool PPCAsmParser::ParseOperand(OperandV
> break;
> }
> }
> - // Fall-through..
> + LLVM_FALLTHROUGH;
>
> default:
> return Error(S, "invalid memory operand");
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Aug 17 00:10:15
> 2016
> @@ -3575,7 +3575,8 @@ void PPCDAGToDAGISel::PeepholeCROps() {
> Op.getOperand(0) == Op.getOperand(1))
> Op2Not = true;
> }
> - } // fallthrough
> + LLVM_FALLTHROUGH;
> + }
> case PPC::BC:
> case PPC::BCn:
> case PPC::SELECT_I4:
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Aug 17 00:10:15
> 2016
> @@ -3748,7 +3748,7 @@ SDValue PPCTargetLowering::LowerFormalAr
> ArgOffset += PtrByteSize;
> break;
> }
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case MVT::i64: // PPC64
> if (GPR_idx != Num_GPR_Regs) {
> unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp Wed Aug 17
> 00:10:15 2016
> @@ -131,12 +131,12 @@ int PPCTTIImpl::getIntImmCost(unsigned O
> return TTI::TCC_Free;
> case Instruction::And:
> RunFree = true; // (for the rotate-and-mask instructions)
> - // Fallthrough...
> + LLVM_FALLTHROUGH;
> case Instruction::Add:
> case Instruction::Or:
> case Instruction::Xor:
> ShiftedFree = true;
> - // Fallthrough...
> + LLVM_FALLTHROUGH;
> case Instruction::Sub:
> case Instruction::Mul:
> case Instruction::Shl:
> @@ -147,7 +147,8 @@ int PPCTTIImpl::getIntImmCost(unsigned O
> case Instruction::ICmp:
> UnsignedFree = true;
> ImmIdx = 1;
> - // Fallthrough... (zero comparisons can use record-form instructions)
> + // Zero comparisons can use record-form instructions.
> + LLVM_FALLTHROUGH;
> case Instruction::Select:
> ZeroFree = true;
> break;
>
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Aug 17 00:10:15 2016
> @@ -182,18 +182,18 @@ getX86ConditionCode(CmpInst::Predicate P
> default: break;
> // Floating-point Predicates
> case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
> - case CmpInst::FCMP_OLT: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
> - case CmpInst::FCMP_OLE: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
> - case CmpInst::FCMP_UGT: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
> - case CmpInst::FCMP_UGE: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
> case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
> case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
> case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
> - case CmpInst::FCMP_OEQ: // fall-through
> + case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
> case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
>
> // Integer Predicates
> @@ -229,15 +229,15 @@ getX86SSEConditionCode(CmpInst::Predicat
> switch (Predicate) {
> default: llvm_unreachable("Unexpected predicate");
> case CmpInst::FCMP_OEQ: CC = 0; break;
> - case CmpInst::FCMP_OGT: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_OGT: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_OLT: CC = 1; break;
> - case CmpInst::FCMP_OGE: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_OGE: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_OLE: CC = 2; break;
> case CmpInst::FCMP_UNO: CC = 3; break;
> case CmpInst::FCMP_UNE: CC = 4; break;
> - case CmpInst::FCMP_ULE: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_ULE: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_UGE: CC = 5; break;
> - case CmpInst::FCMP_ULT: NeedSwap = true; // fall-through
> + case CmpInst::FCMP_ULT: NeedSwap = true; LLVM_FALLTHROUGH;
> case CmpInst::FCMP_UGT: CC = 6; break;
> case CmpInst::FCMP_ORD: CC = 7; break;
> case CmpInst::FCMP_UEQ:
> @@ -518,8 +518,8 @@ bool X86FastISel::X86FastEmitStore(EVT V
> TII.get(X86::AND8ri), AndResult)
> .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
> ValReg = AndResult;
> + LLVM_FALLTHROUGH; // handle i1 as i8.
> }
> - // FALLTHROUGH, handling i1 as i8.
> case MVT::i8: Opc = X86::MOV8mr; break;
> case MVT::i16: Opc = X86::MOV16mr; break;
> case MVT::i32:
> @@ -659,7 +659,9 @@ bool X86FastISel::X86FastEmitStore(EVT V
> bool Signed = true;
> switch (VT.getSimpleVT().SimpleTy) {
> default: break;
> - case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
> + case MVT::i1:
> + Signed = false;
> + LLVM_FALLTHROUGH; // Handle as i8.
> case MVT::i8: Opc = X86::MOV8mi; break;
> case MVT::i16: Opc = X86::MOV16mi; break;
> case MVT::i32: Opc = X86::MOV32mi; break;
> @@ -1601,7 +1603,8 @@ bool X86FastISel::X86SelectBranch(const
> switch (Predicate) {
> default: break;
> case CmpInst::FCMP_OEQ:
> - std::swap(TrueMBB, FalseMBB); // fall-through
> + std::swap(TrueMBB, FalseMBB);
> + LLVM_FALLTHROUGH;
> case CmpInst::FCMP_UNE:
> NeedExtraBranch = true;
> Predicate = CmpInst::FCMP_ONE;
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 17 00:10:15 2016
> @@ -2700,7 +2700,7 @@ SelectInlineAsmMemoryOperand(const SDVal
> case InlineAsm::Constraint_i:
> // FIXME: It seems strange that 'i' is needed here since it's
> supposed to
> // be an immediate and not a memory constraint.
> - // Fallthrough.
> + LLVM_FALLTHROUGH;
> case InlineAsm::Constraint_o: // offsetable ??
> case InlineAsm::Constraint_v: // not offsetable ??
> case InlineAsm::Constraint_m: // memory
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 17 00:10:15 2016
> @@ -7567,7 +7567,7 @@ static SDValue lowerVectorShuffleAsBlend
> case MVT::v4i64:
> case MVT::v8i32:
> assert(Subtarget.hasAVX2() && "256-bit integer blends require AVX2!");
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case MVT::v2i64:
> case MVT::v4i32:
> // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits
> into
> @@ -7583,7 +7583,7 @@ static SDValue lowerVectorShuffleAsBlend
> VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
> DAG.getConstant(BlendMask, DL, MVT::i8)));
> }
> - // FALLTHROUGH
> + LLVM_FALLTHROUGH;
> case MVT::v8i16: {
> // For integer shuffles we need to expand the mask and cast the
> inputs to
> // v8i16s prior to blending.
> @@ -7609,8 +7609,8 @@ static SDValue lowerVectorShuffleAsBlend
> return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
> DAG.getConstant(BlendMask, DL, MVT::i8));
> }
> + LLVM_FALLTHROUGH;
> }
> - // FALLTHROUGH
> case MVT::v16i8:
> case MVT::v32i8: {
> assert((VT.is128BitVector() || Subtarget.hasAVX2()) &&
> @@ -15383,19 +15383,19 @@ static int translateX86FSETCC(ISD::CondC
> case ISD::SETOEQ:
> case ISD::SETEQ: SSECC = 0; break;
> case ISD::SETOGT:
> - case ISD::SETGT: Swap = true; // Fallthrough
> + case ISD::SETGT: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETLT:
> case ISD::SETOLT: SSECC = 1; break;
> case ISD::SETOGE:
> - case ISD::SETGE: Swap = true; // Fallthrough
> + case ISD::SETGE: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETLE:
> case ISD::SETOLE: SSECC = 2; break;
> case ISD::SETUO: SSECC = 3; break;
> case ISD::SETUNE:
> case ISD::SETNE: SSECC = 4; break;
> - case ISD::SETULE: Swap = true; // Fallthrough
> + case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETUGE: SSECC = 5; break;
> - case ISD::SETULT: Swap = true; // Fallthrough
> + case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETUGT: SSECC = 6; break;
> case ISD::SETO: SSECC = 7; break;
> case ISD::SETUEQ:
> @@ -15501,12 +15501,12 @@ static SDValue LowerIntVSETCC_AVX512(SDV
> case ISD::SETNE: SSECC = 4; break;
> case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
> case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
> - case ISD::SETLT: Swap = true; //fall-through
> + case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
> case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
> case ISD::SETULT: SSECC = 1; Unsigned = true; break;
> case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
> case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
> - case ISD::SETULE: Unsigned = true; //fall-through
> + case ISD::SETULE: Unsigned = true; LLVM_FALLTHROUGH;
> case ISD::SETLE: SSECC = 2; break;
> }
>
> @@ -18267,7 +18267,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> case Intrinsic::x86_avx_vtestz_pd:
> case Intrinsic::x86_avx_vtestz_ps_256:
> case Intrinsic::x86_avx_vtestz_pd_256:
> - IsTestPacked = true; // Fallthrough
> + IsTestPacked = true;
> + LLVM_FALLTHROUGH;
> case Intrinsic::x86_sse41_ptestz:
> case Intrinsic::x86_avx_ptestz_256:
> // ZF = 1
> @@ -18277,7 +18278,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> case Intrinsic::x86_avx_vtestc_pd:
> case Intrinsic::x86_avx_vtestc_ps_256:
> case Intrinsic::x86_avx_vtestc_pd_256:
> - IsTestPacked = true; // Fallthrough
> + IsTestPacked = true;
> + LLVM_FALLTHROUGH;
> case Intrinsic::x86_sse41_ptestc:
> case Intrinsic::x86_avx_ptestc_256:
> // CF = 1
> @@ -18287,7 +18289,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> case Intrinsic::x86_avx_vtestnzc_pd:
> case Intrinsic::x86_avx_vtestnzc_ps_256:
> case Intrinsic::x86_avx_vtestnzc_pd_256:
> - IsTestPacked = true; // Fallthrough
> + IsTestPacked = true;
> + LLVM_FALLTHROUGH;
> case Intrinsic::x86_sse41_ptestnzc:
> case Intrinsic::x86_avx_ptestnzc_256:
> // ZF and CF = 0
> @@ -24759,7 +24762,7 @@ void X86TargetLowering::computeKnownBits
> // These nodes' second result is a boolean.
> if (Op.getResNo() == 0)
> break;
> - // Fallthrough
> + LLVM_FALLTHROUGH;
> case X86ISD::SETCC:
> KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
> break;
> @@ -25946,7 +25949,7 @@ combineRedundantDWordShuffle(SDValue N,
>
> Chain.push_back(V);
>
> - // Fallthrough!
> + LLVM_FALLTHROUGH;
> case ISD::BITCAST:
> V = V.getOperand(0);
> continue;
> @@ -27705,7 +27708,7 @@ static bool checkBoolTestAndOrSetCCCombi
> case ISD::AND:
> case X86ISD::AND:
> isAnd = true;
> - // fallthru
> + LLVM_FALLTHROUGH;
> case ISD::OR:
> case X86ISD::OR:
> SetCC0 = Cond->getOperand(0);
> @@ -31675,7 +31678,7 @@ bool X86TargetLowering::IsDesirableToPro
> case ISD::OR:
> case ISD::XOR:
> Commute = true;
> - // fallthrough
> + LLVM_FALLTHROUGH;
> case ISD::SUB: {
> SDValue N0 = Op.getOperand(0);
> SDValue N1 = Op.getOperand(1);
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Aug 17 00:10:15 2016
> @@ -151,13 +151,14 @@ X86RegisterInfo::getLargestLegalSuperCla
> // If VLX isn't support we shouldn't inflate to these classes.
> if (!Subtarget.hasVLX())
> break;
> - // Fallthrough. The VLX check above passed, AVX512 check below will
> pass.
> + // The VLX check above passed, AVX512 check below will pass.
> + LLVM_FALLTHROUGH;
> case X86::VR128XRegClassID:
> case X86::VR256XRegClassID:
> // If AVX-512 isn't support we shouldn't inflate to these classes.
> if (!Subtarget.hasAVX512())
> break;
> - // Fallthrough.
> + LLVM_FALLTHROUGH;
> case X86::GR8RegClassID:
> case X86::GR16RegClassID:
> case X86::GR32RegClassID:
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Wed Aug 17
> 00:10:15 2016
> @@ -1413,7 +1413,7 @@ int X86TTIImpl::getIntImmCost(unsigned O
> // immediates here as the normal path expects bit 31 to be sign
> extended.
> if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32
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