[llvm] r278857 - [x86] Allow merging multiple instances of an immediate within a basic block for code size savings, for 64-bit constants.
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 14:35:16 PDT 2016
Author: spatel
Date: Tue Aug 16 16:35:16 2016
New Revision: 278857
URL: http://llvm.org/viewvc/llvm-project?rev=278857&view=rev
Log:
[x86] Allow merging multiple instances of an immediate within a basic block for code size savings, for 64-bit constants.
This patch handles 64-bit constants which can be encoded as 32-bit immediates.
It extends the functionality added by https://reviews.llvm.org/D11363 for 32-bit constants to 64-bit constants.
Patch by Sunita Marathe!
Differential Revision: https://reviews.llvm.org/D23391
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/CodeGen/X86/immediate_merging64.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=278857&r1=278856&r2=278857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Tue Aug 16 16:35:16 2016
@@ -625,7 +625,7 @@ def Xi32 : X86TypeInfo<i32, "l", GR32, l
Imm32, i32imm, imm32_su, i32i8imm, i32immSExt8_su,
1, OpSize32, 0>;
def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
- Imm32S, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
+ Imm32S, i64i32imm, i64immSExt32_su, i64i8imm, i64immSExt8_su,
1, OpSizeFixed, 1>;
/// ITy - This instruction base class takes the type info for the instruction.
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=278857&r1=278856&r2=278857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Aug 16 16:35:16 2016
@@ -923,6 +923,7 @@ def X86_COND_S : PatLeaf<(i8 15)>;
def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
+def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
// If we have multiple users of an immediate, it's much smaller to reuse
// the register, rather than encode the immediate in every instruction.
@@ -950,6 +951,9 @@ def imm16_su : PatLeaf<(i16 imm), [{
def imm32_su : PatLeaf<(i32 imm), [{
return !shouldAvoidImmediateInstFormsForSize(N);
}]>;
+def i64immSExt32_su : PatLeaf<(i64immSExt32), [{
+ return !shouldAvoidImmediateInstFormsForSize(N);
+}]>;
def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
return !shouldAvoidImmediateInstFormsForSize(N);
@@ -957,10 +961,9 @@ def i16immSExt8_su : PatLeaf<(i16immSExt
def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
return !shouldAvoidImmediateInstFormsForSize(N);
}]>;
-
-
-def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
-
+def i64immSExt8_su : PatLeaf<(i64immSExt8), [{
+ return !shouldAvoidImmediateInstFormsForSize(N);
+}]>;
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
// unsigned field.
@@ -1409,7 +1412,7 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs),
[(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
- [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
+ [(store i64immSExt32_su:$src, addr:$dst)], IIC_MOV_MEM>;
} // SchedRW
let hasSideEffects = 0 in {
Modified: llvm/trunk/test/CodeGen/X86/immediate_merging64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/immediate_merging64.ll?rev=278857&r1=278856&r2=278857&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/immediate_merging64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/immediate_merging64.ll Tue Aug 16 16:35:16 2016
@@ -4,36 +4,20 @@
; Check that multiple instances of 64-bit constants encodable as
; 32-bit immediates are merged for code size savings.
- at g1 = common global i64 0, align 8
- at g2 = common global i64 0, align 8
- at g3 = common global i64 0, align 8
- at g4 = common global i64 0, align 8
-
; Immediates with multiple users should not be pulled into instructions when
; optimizing for code size.
-define void @imm_multiple_users(i64 %l1, i64 %l2, i64 %l3, i64 %l4) optsize {
+define i1 @imm_multiple_users(i64 %a, i64* %b) optsize {
; CHECK-LABEL: imm_multiple_users:
; CHECK: # BB#0:
-; CHECK-NEXT: movq $-1, {{.*}}(%rip)
-; CHECK-NEXT: cmpq $-1, %rdx
-; CHECK-NEXT: cmovneq %rsi, %rdi
-; CHECK-NEXT: movq %rdi, {{.*}}(%rip)
; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: # kill: %CL<def> %CL<kill> %RCX<kill>
-; CHECK-NEXT: shlq %cl, %rax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
-; CHECK-NEXT: movq $0, {{.*}}(%rip)
+; CHECK-NEXT: movq %rax, (%rsi)
+; CHECK-NEXT: cmpq %rax, %rdi
+; CHECK-NEXT: sete %al
; CHECK-NEXT: retq
;
- store i64 -1, i64* @g1, align 8
- %cmp = icmp eq i64 %l3, -1
- %sel = select i1 %cmp, i64 %l1, i64 %l2
- store i64 %sel, i64* @g2, align 8
- %and = and i64 %l4, 63
- %shl = shl i64 -1, %and
- store i64 %shl, i64* @g3, align 8
- store i64 0, i64* @g4, align 8
- ret void
+ store i64 -1, i64* %b, align 8
+ %cmp = icmp eq i64 %a, -1
+ ret i1 %cmp
}
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
@@ -44,11 +28,11 @@ declare void @llvm.memset.p0i8.i64(i8* n
define void @memset_zero(i8* noalias nocapture %D) optsize {
; CHECK-LABEL: memset_zero:
; CHECK: # BB#0:
-; CHECK-NEXT: movq $0, 7(%rdi)
-; CHECK-NEXT: movq $0, (%rdi)
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movq %rax, 7(%rdi)
+; CHECK-NEXT: movq %rax, (%rdi)
; CHECK-NEXT: retq
;
tail call void @llvm.memset.p0i8.i64(i8* %D, i8 0, i64 15, i32 1, i1 false)
ret void
}
-
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