[llvm] r278665 - [AMDGPU] fix failure on printing of non-existing instruction operands.

[Valery Pykhtin via llvm-commits]

Author: vpykhtin
Date: Mon Aug 15 05:56:48 2016
New Revision: 278665

URL: http://llvm.org/viewvc/llvm-project?rev=278665&view=rev
Log:
[AMDGPU] fix failure on printing of non-existing instruction operands.

Differential revision: https://reviews.llvm.org/D23323

Added:
    llvm/trunk/test/MC/Disassembler/AMDGPU/missing_op.txt
Modified:
    llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=278665&r1=278664&r2=278665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Mon Aug 15 05:56:48 2016
@@ -370,6 +370,11 @@ void AMDGPUInstPrinter::printImmediate64
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                      raw_ostream &O) {
 
+  if (OpNo >= MI->getNumOperands()) {
+    O << "/*Missing OP" << OpNo << "*/";
+    return;
+  }
+
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     switch (Op.getReg()) {

Added: llvm/trunk/test/MC/Disassembler/AMDGPU/missing_op.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/missing_op.txt?rev=278665&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/missing_op.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/missing_op.txt Mon Aug 15 05:56:48 2016
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI
+
+#TODO: this test will fail when we fix v_interp_p2_f32 signature, remove it then
+#VI: v_interp_p2_f32 16, [/*Missing OP1*/], /*Missing OP2*/, /*Missing OP3*/, /*Missing OP4*/
+0xd4 0x41 0x1d 0xd4