[PATCH] D23172: Treat aliased registers as live in if-conversion

[Jonas Paulsson via llvm-commits]

jonpa added a comment.

>From what I can understand, the MachineFunction has first the %R16 and %R17 defined in BB#0, to be later used in BB#2. This is why these registers are the ones present in 
the live-in lists to begin with, and not %https://reviews.llvm.org/D8. Then, the Hexagon Copy-To-Combine pass rewrites BB#0, to copy %https://reviews.llvm.org/D8 with one instruction. The live-in lists remain the same, and the use operands also:

(abbreviated)

  BB#0: derived from LLVM BB %entry
      Live Ins: %R0 %R1 %D8 %D8
  	%R16<def> = A2_tfr %R1<kill>
  	%R17<def> = A2_tfr %R0<kill>
      Successors according to CFG: BB#3(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%)
  
  BB#1: derived from LLVM BB %for.body.preheader
      Live Ins: %R16 %R17
      Predecessors according to CFG: BB#0
      Successors according to CFG: BB#2(?%)
  
  BB#2: derived from LLVM BB %for.body
      Live Ins: %D2 %R16 %R17 %R29 %R30 %R31
      Predecessors according to CFG: BB#1 BB#2
  	%R17<def> = A2_addi %R17<kill>, -1
  	%R16<def> = A2_addi %R16<kill>, 8
  
  -> # After Hexagon Copy-To-Combine Pass:
  
  BB#0: derived from LLVM BB %entry
      Live Ins: %R0 %R1 %D8 %D8
  	%D8<def> = A2_combinew %R0<kill>, %R1<kill>
  
  BB#1: derived from LLVM BB %for.body.preheader
      Live Ins: %R16 %R17
      Predecessors according to CFG: BB#0
      Successors according to CFG: BB#2(?%)
  
  BB#2: derived from LLVM BB %for.body
      Live Ins: %D2 %R16 %R17 %R29 %R30 %R31
  	%R17<def> = A2_addi %R17<kill>, -1
  	%R16<def> = A2_addi %R16<kill>, 8

The first question for me is if this transformation is entirely correct. Should also implicit-defs of %R16 or %R17 be added to the new instruction? Or should it add %https://reviews.llvm.org/D8 to live-in lists and as implicit-use operands? (The latter alternative seems discouraging due to its complexity).

This patch seems conservatively right though in this context to assume that %https://reviews.llvm.org/D8 is live when any one of its subregs is live (it will make LivePhysRegs in later passes think that all of the subregs are live.)

Quentin, what do you think?


Repository:
  rL LLVM

https://reviews.llvm.org/D23172