[llvm] r277329 - [SimplifyCFG] Try and pacify buildbots after r277325

[Benjamin Kramer via llvm-commits]

If you see this happening ever again don't fix the test case. IR
generation is supposed to be deterministic. Random reorderings are a
bug in your code that shouldn't be papered over with CHECK-DAGs.

On Mon, Aug 1, 2016 at 10:09 AM, James Molloy via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: jamesm
> Date: Mon Aug  1 03:09:55 2016
> New Revision: 277329
>
> URL: http://llvm.org/viewvc/llvm-project?rev=277329&view=rev
> Log:
> [SimplifyCFG] Try and pacify buildbots after r277325
>
> It looks like the two independent parts of the rotate operation (a lshr and shl) are being reordered on some bots. Add CHECK-DAGs to account for this.
>
> Modified:
>     llvm/trunk/test/Transforms/SimplifyCFG/rangereduce.ll
>
> Modified: llvm/trunk/test/Transforms/SimplifyCFG/rangereduce.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/rangereduce.ll?rev=277329&r1=277328&r2=277329&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/SimplifyCFG/rangereduce.ll (original)
> +++ llvm/trunk/test/Transforms/SimplifyCFG/rangereduce.ll Mon Aug  1 03:09:55 2016
> @@ -4,8 +4,8 @@ target datalayout = "e-n32"
>
>  ; CHECK-LABEL: @test1
>  ; CHECK: %1 = sub i32 %a, 97
> -; CHECK: %2 = lshr i32 %1, 2
> -; CHECK: %3 = shl i32 %1, 30
> +; CHECK-DAG: %2 = lshr i32 %1, 2
> +; CHECK-DAG: %3 = shl i32 %1, 30
>  ; CHECK: %4 = or i32 %2, %3
>  ; CHECK:  switch i32 %4, label %def [
>  ; CHECK:    i32 0, label %one
> @@ -121,8 +121,8 @@ three:
>
>  ; CHECK-LABEL: @test6
>  ; CHECK: %1 = sub i32 %a, -109
> -; CHECK: %2 = lshr i32 %1, 2
> -; CHECK: %3 = shl i32 %1, 30
> +; CHECK-DAG: %2 = lshr i32 %1, 2
> +; CHECK-DAG: %3 = shl i32 %1, 30
>  ; CHECK: %4 = or i32 %2, %3
>  ; CHECK:  switch i32 %4, label %def [
>  define i32 @test6(i32 %a) optsize {
> @@ -146,8 +146,8 @@ three:
>
>  ; CHECK-LABEL: @test7
>  ; CHECK: %1 = sub i8 %a, -36
> -; CHECK: %2 = lshr i8 %1, 2
> -; CHECK: %3 = shl i8 %1, 6
> +; CHECK-DAG: %2 = lshr i8 %1, 2
> +; CHECK-DAG: %3 = shl i8 %1, 6
>  ; CHECK: %4 = or i8 %2, %3
>  ; CHECK:  switch.tableidx = {{.*}} %4
>  define i8 @test7(i8 %a) optsize {
> @@ -171,8 +171,8 @@ three:
>
>  ; CHECK-LABEL: @test8
>  ; CHECK: %1 = sub i32 %a, 97
> -; CHECK: %2 = lshr i32 %1, 2
> -; CHECK: %3 = shl i32 %1, 30
> +; CHECK-DAG: %2 = lshr i32 %1, 2
> +; CHECK-DAG: %3 = shl i32 %1, 30
>  ; CHECK: %4 = or i32 %2, %3
>  ; CHECK:  switch i32 %4, label %def [
>  define i32 @test8(i32 %a) optsize {
>
>
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