[PATCH] D22632: Wrong code generation for VSX floating-point loads with fast-isel

[Ulrich Weigand via llvm-commits]

uweigand marked an inline comment as done.

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Comment at: lib/Target/PowerPC/PPCFastISel.cpp:524-525
@@ -523,4 +523,4 @@
   // be used.
-  bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
-  bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
+  bool IsVSSRC = isVSSRCRegClass(UseRC);
+  bool IsVSFRC = isVSFRCRegClass(UseRC);
   bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
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OK, I've changed the helper routines to take a regclass instead of a register.  This means we don't even need to move the initialization of ResultReg, since UseRC is already set up correctly in either case here.


https://reviews.llvm.org/D22632