[llvm] r277775 - GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 4 14:39:49 PDT 2016
Author: tnorthover
Date: Thu Aug 4 16:39:49 2016
New Revision: 277775
URL: http://llvm.org/viewvc/llvm-project?rev=277775&view=rev
Log:
GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.
These are the operations that are trivially identical. Division is omitted for
now because you need to use the correct sign/zero extension.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp?rev=277775&r1=277774&r2=277775&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp Thu Aug 4 16:39:49 2016
@@ -100,7 +100,12 @@ MachineLegalizeHelper::widenScalar(Machi
switch (MI.getOpcode()) {
default:
return UnableToLegalize;
- case TargetOpcode::G_ADD: {
+ case TargetOpcode::G_ADD:
+ case TargetOpcode::G_AND:
+ case TargetOpcode::G_MUL:
+ case TargetOpcode::G_OR:
+ case TargetOpcode::G_XOR:
+ case TargetOpcode::G_SUB: {
// Perform operation at larger width (any extension is fine here, high bits
// don't affect the result) and then truncate the result back to the
// original type.
@@ -114,7 +119,8 @@ MachineLegalizeHelper::widenScalar(Machi
MIRBuilder.buildAnyExtend(WideTy, Src2Ext, MI.getOperand(2).getReg());
unsigned DstExt = MRI.createGenericVirtualRegister(WideSize);
- MIRBuilder.buildAdd(WideTy, DstExt, Src1Ext, Src2Ext);
+ MIRBuilder.buildInstr(MI.getOpcode(), WideTy)
+ .addDef(DstExt).addUse(Src1Ext).addUse(Src2Ext);
MIRBuilder.buildTrunc(MI.getType(), MI.getOperand(0).getReg(), DstExt);
MI.eraseFromParent();
Modified: llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp?rev=277775&r1=277774&r2=277775&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp Thu Aug 4 16:39:49 2016
@@ -34,7 +34,7 @@ AArch64MachineLegalizer::AArch64MachineL
const LLT v4s32 = LLT::vector(4, 32);
const LLT v2s64 = LLT::vector(2, 64);
- for (auto BinOp : {G_ADD, G_SUB, G_AND, G_OR, G_XOR}) {
+ for (auto BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
for (auto Ty : {s32, s64, v2s32, v4s32, v2s64})
setAction(BinOp, Ty, Legal);
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=277775&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Thu Aug 4 16:39:49 2016
@@ -0,0 +1,32 @@
+# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-apple-ios"
+ define void @test_scalar_and_small() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_scalar_and_small
+isSSA: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0.entry:
+ liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_scalar_and_small
+ ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXTEND s32 %0
+ ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXTEND s32 %1
+ ; CHECK: [[RES:%.*]](32) = G_AND s32 [[LHS]], [[RHS]]
+ ; CHECK: %2(8) = G_TRUNC s8 [[RES]]
+
+ %0(8) = G_TRUNC s8 %x0
+ %1(8) = G_TRUNC s8 %x1
+ %2(8) = G_AND s8 %0, %1
+ %x0 = G_ANYEXTEND s64 %2
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=277775&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Thu Aug 4 16:39:49 2016
@@ -0,0 +1,32 @@
+# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-apple-ios"
+ define void @test_scalar_mul_small() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_scalar_mul_small
+isSSA: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0.entry:
+ liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_scalar_mul_small
+ ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXTEND s32 %0
+ ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXTEND s32 %1
+ ; CHECK: [[RES:%.*]](32) = G_MUL s32 [[LHS]], [[RHS]]
+ ; CHECK: %2(8) = G_TRUNC s8 [[RES]]
+
+ %0(8) = G_TRUNC s8 %x0
+ %1(8) = G_TRUNC s8 %x1
+ %2(8) = G_MUL s8 %0, %1
+ %x0 = G_ANYEXTEND s64 %2
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=277775&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Thu Aug 4 16:39:49 2016
@@ -0,0 +1,32 @@
+# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-apple-ios"
+ define void @test_scalar_or_small() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_scalar_or_small
+isSSA: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0.entry:
+ liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_scalar_or_small
+ ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXTEND s32 %0
+ ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXTEND s32 %1
+ ; CHECK: [[RES:%.*]](32) = G_OR s32 [[LHS]], [[RHS]]
+ ; CHECK: %2(8) = G_TRUNC s8 [[RES]]
+
+ %0(8) = G_TRUNC s8 %x0
+ %1(8) = G_TRUNC s8 %x1
+ %2(8) = G_OR s8 %0, %1
+ %x0 = G_ANYEXTEND s64 %2
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir?rev=277775&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir Thu Aug 4 16:39:49 2016
@@ -0,0 +1,32 @@
+# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-apple-ios"
+ define void @test_scalar_sub_small() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_scalar_sub_small
+isSSA: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0.entry:
+ liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_scalar_sub_small
+ ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXTEND s32 %0
+ ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXTEND s32 %1
+ ; CHECK: [[RES:%.*]](32) = G_SUB s32 [[LHS]], [[RHS]]
+ ; CHECK: %2(8) = G_TRUNC s8 [[RES]]
+
+ %0(8) = G_TRUNC s8 %x0
+ %1(8) = G_TRUNC s8 %x1
+ %2(8) = G_SUB s8 %0, %1
+ %x0 = G_ANYEXTEND s64 %2
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=277775&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Thu Aug 4 16:39:49 2016
@@ -0,0 +1,32 @@
+# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-apple-ios"
+ define void @test_scalar_xor_small() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_scalar_xor_small
+isSSA: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0.entry:
+ liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_scalar_xor_small
+ ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXTEND s32 %0
+ ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXTEND s32 %1
+ ; CHECK: [[RES:%.*]](32) = G_XOR s32 [[LHS]], [[RHS]]
+ ; CHECK: %2(8) = G_TRUNC s8 [[RES]]
+
+ %0(8) = G_TRUNC s8 %x0
+ %1(8) = G_TRUNC s8 %x1
+ %2(8) = G_XOR s8 %0, %1
+ %x0 = G_ANYEXTEND s64 %2
+...
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