[llvm] r277749 - GlobalISel: also add G_TRUNC to IRTranslator.

Tim Northover via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 4 11:35:17 PDT 2016


Author: tnorthover
Date: Thu Aug  4 13:35:17 2016
New Revision: 277749

URL: http://llvm.org/viewvc/llvm-project?rev=277749&view=rev
Log:
GlobalISel: also add G_TRUNC to IRTranslator.

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=277749&r1=277748&r2=277749&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Aug  4 13:35:17 2016
@@ -252,13 +252,15 @@ bool IRTranslator::translate(const Instr
   case Instruction::Call:
     return translateCall(cast<CallInst>(Inst));
 
-  // Casts
+  // Casts and allied operations
   case Instruction::BitCast:
     return translateBitCast(cast<CastInst>(Inst));
   case Instruction::IntToPtr:
     return translateCast(TargetOpcode::G_INTTOPTR, cast<CastInst>(Inst));
   case Instruction::PtrToInt:
     return translateCast(TargetOpcode::G_PTRTOINT, cast<CastInst>(Inst));
+  case Instruction::Trunc:
+    return translateCast(TargetOpcode::G_TRUNC, cast<CastInst>(Inst));
 
   // Memory ops.
   case Instruction::Load:

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=277749&r1=277748&r2=277749&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Aug  4 13:35:17 2016
@@ -223,6 +223,19 @@ define i64 @bitcast(i64 %a) {
   ret i64 %res2
 }
 
+; CHECK-LABEL: name: trunc
+; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
+; CHECK: [[VEC:%[0-9]+]](128) = G_LOAD { <4 x s32>, p0 }
+; CHECK: [[RES1:%[0-9]+]](8) = G_TRUNC { s8, s64 } [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]](64) = G_TRUNC { <4 x s16>, <4 x s32> } [[VEC]]
+define void @trunc(i64 %a) {
+  %vecptr = alloca <4 x i32>
+  %vec = load <4 x i32>, <4 x i32>* %vecptr
+  %res1 = trunc i64 %a to i8
+  %res2 = trunc <4 x i32> %vec to <4 x i16>
+  ret void
+}
+
 ; CHECK-LABEL: name: load
 ; CHECK: [[ADDR:%[0-9]+]](64) = COPY %x0
 ; CHECK: [[ADDR42:%[0-9]+]](64) = COPY %x1




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