[llvm] r277626 - [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Aug  3 13:35:48 2016
New Revision: 277626

URL: http://llvm.org/viewvc/llvm-project?rev=277626&view=rev
Log:
[Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
    llvm/trunk/test/CodeGen/Hexagon/combine.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=277626&r1=277625&r2=277626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Wed Aug  3 13:35:48 2016
@@ -363,24 +363,28 @@ bool HexagonBitSimplify::replaceSubWithS
 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
       unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI) {
   const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
-  if (RC == &Hexagon::IntRegsRegClass) {
-    assert(RR.Sub == 0);
+  if (RR.Sub == 0) {
     Begin = 0;
-    Width = 32;
+    Width = RC->getSize()*8;
     return true;
   }
-  if (RC == &Hexagon::DoubleRegsRegClass) {
-    if (RR.Sub == 0) {
-      Begin = 0;
-      Width = 64;
-      return true;
-    }
-    assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
-    Width = 32;
-    Begin = (RR.Sub == Hexagon::subreg_loreg ? 0 : 32);
-    return true;
+
+  assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
+  if (RR.Sub == Hexagon::subreg_loreg)
+    Begin = 0;
+
+  switch (RC->getID()) {
+    case Hexagon::DoubleRegsRegClassID:
+    case Hexagon::VecDblRegsRegClassID:
+    case Hexagon::VecDblRegs128BRegClassID:
+      Width = RC->getSize()*8 / 2;
+      if (RR.Sub == Hexagon::subreg_hireg)
+        Begin = Width;
+      break;
+    default:
+      return false;
   }
-  return false;
+  return true;
 }
 
 
@@ -1473,7 +1477,7 @@ namespace {
     CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
         : Transformation(false), MRI(mri) {}
     bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
-    static bool isCopyReg(unsigned Opc);
+    static bool isCopyReg(unsigned Opc, bool NoConv);
   private:
     bool propagateRegCopy(MachineInstr &MI);
 
@@ -1548,7 +1552,8 @@ bool CopyGeneration::processBlock(Machin
     HBS::getInstrDefs(*I, Defs);
 
     unsigned Opc = I->getOpcode();
-    if (CopyPropagation::isCopyReg(Opc) || ConstGeneration::isTfrConst(*I))
+    if (CopyPropagation::isCopyReg(Opc, false) ||
+        ConstGeneration::isTfrConst(*I))
       continue;
 
     DebugLoc DL = I->getDebugLoc();
@@ -1595,18 +1600,19 @@ bool CopyGeneration::processBlock(Machin
 }
 
 
-bool CopyPropagation::isCopyReg(unsigned Opc) {
+bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
   switch (Opc) {
     case TargetOpcode::COPY:
     case TargetOpcode::REG_SEQUENCE:
+    case Hexagon::A4_combineir:
+    case Hexagon::A4_combineri:
+      return true;
     case Hexagon::A2_tfr:
     case Hexagon::A2_tfrp:
     case Hexagon::A2_combinew:
-    case Hexagon::A4_combineir:
-    case Hexagon::A4_combineri:
     case Hexagon::V6_vcombine:
     case Hexagon::V6_vcombine_128B:
-      return true;
+      return NoConv;
     default:
       break;
   }
@@ -1675,7 +1681,7 @@ bool CopyPropagation::processBlock(Machi
   bool Changed = false;
   for (auto I : Instrs) {
     unsigned Opc = I->getOpcode();
-    if (!CopyPropagation::isCopyReg(Opc))
+    if (!CopyPropagation::isCopyReg(Opc, true))
       continue;
     Changed |= propagateRegCopy(*I);
   }

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=277626&r1=277625&r2=277626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Wed Aug  3 13:35:48 2016
@@ -679,6 +679,8 @@ bool HexagonEvaluator::evaluate(const Ma
     case A4_combineir:
     case A4_combineri:
     case A2_combinew:
+    case V6_vcombine:
+    case V6_vcombine_128B:
       assert(W0 % 2 == 0);
       return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
     case A2_combine_ll:

Modified: llvm/trunk/test/CodeGen/Hexagon/combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/combine.ll?rev=277626&r1=277625&r2=277626&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/combine.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/combine.ll Wed Aug  3 13:35:48 2016
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
 ; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
 
 @j = external global i32